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Using the Xeon Phi Platform to Run Speculatively-Parallelized Codes

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Abstract

Intel Xeon Phi accelerators are one of the newest devices used in the field of parallel computing. However, there are comparatively few studies concerning their performance when using most of the existing parallelization techniques. One of them is thread-level speculation, a technique that optimistically tries to extract parallelism of loops without the need of a compile-time analysis that guarantees that the loop can be executed in parallel. In this article we evaluate the performance delivered by an Intel Xeon Phi coprocessor when using a software, state-of-the-art thread-level speculative parallelization library in the execution of well-known benchmarks. We describe both the internal characteristics of the Xeon Phi platform and the particularities of the thread-level speculation library being used as benchmark. Our results show that, although the Xeon Phi delivers a relatively good speedup in comparison with a shared-memory architecture in terms of scalability, the relatively low computing power of its computational units when specific vectorization and SIMD instructions are not fully exploited makes this first generation of Xeon Phi architectures not competitive (in terms of absolute performance) with respect to conventional multicore systems for the execution of speculatively parallelized code.

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Notes

  1. This issue can be addressed by the programmer, or by the use of specific compilers such as [4].

  2. A thread is the simplest unit of execution, intended to process a specific code. A block is defined as a group of threads, where threads can be executed concurrently or sequentially with no order. At this level, a block allow the coordination of its threads with the use of barriers. A grid is a group of blocks without any possible synchronization among them.

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Acknowledgments

This research is partly supported by the Castilla-Leon Regional Government (VA172A12-2); MICINN (Spain) and the European Union FEDER (MOGECOPP project TIN2011-25639, HomProg-HetSys project TIN2014-58876-P, CAPAP-H5 network TIN2014-53522-REDT).

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  1. Departamento de Informatica, Universidad de Valladolid, Campus M. Delibes, 47011, Valladolid, Spain

    Alvaro Estebanez, Diego R. Llanos & Arturo Gonzalez-Escribano

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  1. Alvaro Estebanez
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Correspondence to Diego R. Llanos.

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Estebanez, A., Llanos, D.R. & Gonzalez-Escribano, A. Using the Xeon Phi Platform to Run Speculatively-Parallelized Codes. Int J Parallel Prog 45, 225–241 (2017). https://doi.org/10.1007/s10766-016-0421-x

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