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A new representation in 3D VLSI floorplan: 3D O-Tree

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Abstract

The size of the implemented circuit plays a vital role in maximizing the performance of the chip. Hence, researchers are looking to utilize the extra dimension to improve performance, which requires the development of new methods and techniques for efficient implementation. This paper proposes a new, simple, efficient representation in 3D VLSI Floorplan named 3D O-Tree representation for Electronic Design Automation (EDA). Since the 3D floorplan packing problem is NP-hard (Nondeterministic Polynomial time), the novel representation is accompanied with an adaptive modified Memetic Algorithm with a kill strategy for fast performance. The tool presented in this paper employs Genetic Algorithm for global exploration, and an improved compatible local technique is used to exploit promising search regions for an improved solution. This representation has been found to be effective in obtaining an efficient packed 3D floorplan. In the case of okp benchmarks, the proposed algorithm has achieved the best stated minimum volume yet for okp1 and okp3 benchmarks with 4.62% and 1.87% improvement respectively. The rest of the okp benchmarks have achieved near-to-best previous results. When checked on four standard Beasley benchmarks, better floorplans have been achieved with the proposed representation. They are found to be more effective and efficient than the current state-of-the-art research, with a range of 1.6% to 9.29% improvement as compared to the volume of the previous best-reported results. Beasley 7 retains the previous best solution in terms of volume, improving significantly in time to achieve the solution. Also, the required optimization time is reduced substantially to achieve the best previous results. The statistical analysis also shows the efficacy of the proposed technique.

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Acknowledgements

The authors would like to extend gratitude to Dean RIC, I. K. Gujral, Punjab Technical University, Kapurthala, for support in the completion of this research work.

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  1. Department of Electronics and Communication Engineering, I.K. Gujral Punjab Technical University, Kapurthala, Punjab, 144603, India

    Rohin Gupta

  2. Department of Electronics and Communication Engineering, National Institute of Technical Teachers Training and Research, Chandigarh, 160019, India

    Sandeep Singh Gill

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Gupta, R., Gill, S.S. A new representation in 3D VLSI floorplan: 3D O-Tree. Genet Program Evolvable Mach 25, 12 (2024). https://doi.org/10.1007/s10710-024-09485-3

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