Comparing three online evolvable hardware implementations of a classification system

Article
  • 115 Downloads

Abstract

In this paper, we present three implementations of an online evolvable hardware classifier of sonar signals on a 28 nm process technology FPGA, and compare their features using the most relevant metrics in the design of hardware: area, timing, power consumption, energy consumption, and performance. The three implementations are: one full-hardware implementation in which all the modules of the evolvable hardware system, the evaluation module and the Evolutionary Algorithm have been implemented on the ZedBoard™ Zynq® Evaluation Kit (XC7-Z020 ELQ484-1); and two hardware/software implementations in which the Evolutionary Algorithm has been implemented in software and run on two different processors: Zynq® XC7-Z020 and MicroBlaze™. Additionally, each processor-based implementation has been tested at several processor speeds. The results prove that the full-hardware implementation always performs better than the hardware/software implementations by a considerable margin: up to \(\times \,7.74\) faster than MicroBlaze, between \(\times \,1.39\) and \(\times \,2.11\) faster that Zynq, and \(\times \,0.198\) lower power consumption. However, the hardware/software implementations have the advantage of being more flexible for testing different options during the design phase. These figures can be used as a guideline to determine the best use for each kind of implementation.

Keywords

Evolutionary algorithms Evolvable hardware Classifier system Field programmable gate arrays 

Notes

Acknowledgements

This work is supported by the Spanish Research Grant TIN2015-65460-C2, and NILS Grant ABEL-IM-2014A.

References

  1. 1.
    A. Balleri, Biologically inspired radar and sonar target classification. Ph.D. thesis, UCL (University College London) (2010)Google Scholar
  2. 2.
    B. Blodget, P. James-Roxby, E. Keller, S. McMillan, P. Sundararajan, A Self-Reconfiguring Platform (Springer, Berlin, 2003), pp. 565–574. doi: 10.1007/978-3-540-45234-8_55 Google Scholar
  3. 3.
    H. Brighton, C. Mellish, Advances in instance selection for instance-based learning algorithms. Data Min. Knowl. Discov. 6(2), 153–172 (2002)MathSciNetCrossRefMATHGoogle Scholar
  4. 4.
    F. Cancare, D.B. Bartolini, M. Carminati, D. Sciuto, M.D. Santambrogio, On the evolution of hardware circuits via reconfigurable architectures. ACM Trans. Reconfigurable Technol. Syst. 5(4), 22:1–22:22 (2012). doi: 10.1145/2392616.2392620 CrossRefGoogle Scholar
  5. 5.
    F. Cancare, M.D. Santambrogio, D. Sciuto, A direct bitstream manipulation approach for virtex4-based evolvable systems, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (2010), pp. 853–856. doi: 10.1109/ISCAS.2010.5537429
  6. 6.
    R. Dobai, L. Sekanina, Towards evolvable systems based on the xilinx zynq platform, in 2013 IEEE International Conference on Evolvable Systems (ICES) (2013), pp. 89–95. doi: 10.1109/ICES.2013.6613287
  7. 7.
    R. Dobai, L. Sekanina, Low-level flexible architecture with hybrid reconfiguration for evolvable hardware. ACM Trans. Reconfigurable Technol. Syst. 8(3), 20:1–20:24 (2015). doi: 10.1145/2700414 CrossRefGoogle Scholar
  8. 8.
    K. Glette, Design and implementation of scalable online evolvable hardware pattern recognition systems. Ph.D. thesis, Faculty of Mathematics and Natural Sciences, University of Oslo, The address of the publisher (2008). An optional noteGoogle Scholar
  9. 9.
    K. Glette, P. Kaufmann, C. Assad, M.T. Wolf, Investigating evolvable hardware classification for the biosleeve electromyographic interface, in 2013 IEEE International Conference on Evolvable Systems (ICES) (IEEE, Washigton, 2013), pp. 73–80. doi: 10.1109/ICES.2013.6613285. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6613285
  10. 10.
    K. Glette, J. Torresen, P. Kaufmann, M. Platzner, A comparison of evolvable hardware architectures for classification tasks, in Evolvable Systems: From Biology to Hardware, Lecture Notes in Computer Science, vol. 5216 (Springer, Berlin, 2008), pp. 22–33. doi: 10.1007/978-3-540-85857-7_3. http://link.springer.com/10.1007/978-3-540-85857-7_3
  11. 11.
    K. Glette, J. Torresen, P. Kaufmann, M. Platzner, A Comparison of Evolvable Hardware Architectures for Classification Tasks (Springer, Berlin, 2008), pp. 22–33. doi: 10.1007/978-3-540-85857-7_3 Google Scholar
  12. 12.
    K. Glette, J. Torresen, M. Yasunaga, An online EHW pattern recognition system applied to sonar spectrum classification, in Proceedings of the 7th International Conference on Evolvable Systems: From Biology to Hardware, Lecture Notes in Computer Science, vol. 4684 (Springer, Berlin, 2007), pp. 1–12. doi: 10.1007/978-3-540-74626-3_1. http://link.springer.com/10.1007/978-3-540-74626-3_1
  13. 13.
    R.P. Gorman, T.J. Sejnowski, Analysis of hidden units in a layered network trained to classify sonar targets. Neural Netw. 1(1), 75–89 (1988). doi: 10.1016/0893-6080(88)90023-8. http://www.sciencedirect.com/science/article/pii/0893608088900238
  14. 14.
    G.W. Greenwood, A.M. Tyrrell, Introduction to Evolvable Hardware: A Practical Guide for Designing Self-Adaptive Systems. IEEE Press Series on Computational Intelligence (Wiley, New York, 2006)CrossRefGoogle Scholar
  15. 15.
    K.A.D. Jong, Evolutionary Computation: A Unified Approach (MIT Press, Cambridge, 2006). https://books.google.co.in/books?id=OIRQAAAAMAAJ
  16. 16.
    P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. Torresen, B. Sick, Classification of electromyographic signals: comparing evolvable hardware to conventional classifiers. IEEE Trans. Evol. Comput. 17(1), 46–63 (2013). doi: 10.1109/TEVC.2012.2185845 CrossRefGoogle Scholar
  17. 17.
    S.Y. Lee, J.H. Hong, C.H. Hsieh, M.C. Liang, S.Y.C. Chien, K.H. Lin, Low-power wireless ECG acquisition and classification system for body sensor networks. IEEE J. Biomed. Health Inform. 19(1), 236–246 (2015). doi: 10.1109/JBHI.2014.2310354 CrossRefGoogle Scholar
  18. 18.
    B. López, J. Valverde, E. de la Torre, T. Riesgo, Power-aware multi-objective evolvable hardware system on an fpga, in 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) (2014), pp. 61–68. doi: 10.1109/AHS.2014.6880159
  19. 19.
    P. Martin, An analysis of random number generators for a hardware implementation of genetic programming using FPGAs and Handel-C, in Proceedings of the Genetic and Evolutionary Computation Conference, GECCO ’02 (Morgan Kaufmann Publishers Inc., San Francisco, 2002), pp. 837–844. http://dl.acm.org/citation.cfm?id=646205.682460
  20. 20.
    J. Mora, A. Otero, E. de la Torre, T. Riesgo, Fast and compact evolvable systolic arrays on dynamically reconfigurable fpgas, in 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (2015), pp. 1–7. doi: 10.1109/ReCoSoC.2015.7238087
  21. 21.
    R. Salvador, Evolvable hardware in fpgas: embedded tutorial, in 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) (2016), pp. 1–6. doi: 10.1109/DTIS.2016.7483877
  22. 22.
    D. Schellekens, B. Preneel, I. Verbauwhede, FPGA vendor agnostic true random number generator, in International Conference on Field Programmable Logic and Applications, 2006, FPL ’06 (2006), pp. 1–6. doi: 10.1109/FPL.2006.311206
  23. 23.
    T. Sejnowski, R.P. Gorman, CMU neural networks benchmark collection (1995). http://www.cs.cmu.edu/afs/cs/project/ai-repository/ai/areas/neural/bench/cmu/
  24. 24.
    L. Sekanina, Image filter design with evolvable hardware, in Proceedings on Applications of Evolutionary Computing, Lecture Notes in Computer Science (Springer, Berlin, 2002), pp. 255–266. doi: 10.1007/3-540-46004-7_26
  25. 25.
    L. Sekanina, Evolvable Components: From Theory to Hardware Implementations, Natural Computing Series (Springer, Berlin, 2003)MATHGoogle Scholar
  26. 26.
    Y. Shi, R.C. Eberhart, Fuzzy adaptive particle swarm optimization, in Proceedings of the 2001 Congress on Evolutionary Computation, vol. 1 (2001), pp. 101–106 . doi: 10.1109/CEC.2001.934377
  27. 27.
    E. Stomeo, T. Kalganova, C. Lambert, Chose the right mutation rate for better evolve combinational logic circuits. Int. J. Comput. Intell. 2(2), 277–286 (2006)Google Scholar
  28. 28.
    J. Torresen, Evolvable hardware: a short introduction, in Proceedings of the 1997 International Conference on Neural Information Processing and Intelligent Information Systems, vol. 1 (1997), pp. 674–677Google Scholar
  29. 29.
    J. Torresen, Incremental evolution of a signal classification hardware architecture for prosthetic hand control. KES J. 12(3), 187–199 (2008). http://content.iospress.com/articles/international-journal-of-knowledge-based-and-intelligent-engineering-systems/kes00160
  30. 30.
    J. Torresen, G.A. Senland, K. Glette, Partial reconfiguration applied in an on-line evolvable pattern recognition system, in NORCHIP 2008 (2008), pp. 61–64Google Scholar
  31. 31.
    R.J. Urbanowicz, J.H. Moore, Learning classifier systems: a complete introduction, review, and roadmap. J. Artif. Evol. App. 2009, 1:1–1:25 (2009). doi: 10.1155/2009/736398 Google Scholar
  32. 32.
    Z. Vašíček, L. Sekanina, Hardware accelerator of Cartesian genetic programming with multiple fitness units. Comput. Inform. 29(6), 1359–1371 (2010)MATHGoogle Scholar
  33. 33.
    Z. Vašíček, L. Sekanina, Evolutionary approach to approximate digital circuits design. IEEE Trans. Evol. Comput. 19(3), 432–444 (2015). doi: 10.1109/TEVC.2014.2336175. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6848841
  34. 34.
    Z. Vašíček, M. Žádník, L. Sekanina, J. Tobola, On Evolutionary Synthesis of Linear Transforms in FPGA (Springer, Berlin, 2008), pp. 141–152. doi: 10.1007/978-3-540-85857-7_13 Google Scholar
  35. 35.
    J. Wang, Q.S. Chen, C.H. Lee, Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware. IET Comput. Digit. Tech. 2(5), 386–400 (2008). doi: 10.1049/iet-cdt:20070124 CrossRefGoogle Scholar
  36. 36.
    R. Ward, T. Molteno, Table of linear feedback shift registers. Tech. rep., Department of Physics, University of Otago, Box 56, Dunedin, New Zealand (2007)Google Scholar
  37. 37.
    X. Yao, T. Higuchi, Promises and challenges of evolvable hardware. IEEE Trans. Syst., Man, Cybern. C 29(1), 87–97 (1999). doi: 10.1109/5326.740672. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=740672

Copyright information

© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  1. 1.Dpto. Arquitectura de ComputadoresUniversidad Complutense de MadridMadridSpain
  2. 2.Department of InformaticsUniversity of OsloOsloNorway

Personalised recommendations