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Formal Methods in System Design

, Volume 51, Issue 2, pp 395–418 | Cite as

A methodology to take credit for high-level verification during RTL verification

  • Frederic Doucet
  • Robert Kurshan
Article
  • 119 Downloads

Abstract

High-level verification and synthesis of SystemC models has become increasingly popular as a means to reduce the high RTL verification cost of today’s complex designs. However, the saving derived from performing verification at a higher level of abstraction is largely negated if the RTL then must be completely reverified. We demonstrate how global (system-level) properties may be verified at a behavioral level in a manner that reduces the required RTL verification. Our methodology entails using high-level control models together with semantic stubs for control and data-path refinements. The consequence is that cover goals met during high-level verification are then “virtually” met (in a semantically sound fashion) for RTL verification, and need not be re-established in the RTL. Moreover, it can be significantly more efficient (in terms of required verification cycles) to meet these cover goals at the higher level. This can lead both to less costly verification and earlier debug, providing a better structured, faster and more reliable path to implementation than is possible through conventional RTL verification.

Keywords

SystemC High-level synthesis Micro-architecture High-level verification Coverage Abstraction Refinement 

Notes

Acknowledgements

We thank the reviewers for their very helpful suggestions.

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Copyright information

© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  1. 1.Qualcomm Technologies, Inc.San JoseUSA
  2. 2.New YorkUSA

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