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Selective register-file cache: an energy saving technique for embedded processor architecture

Abstract

Embedded system applications of present-day scenario consume profound energy in execution and its significant fraction is due to an intensive register-file access in the processor architecture. This paper presents a novel architecture incorporating a multi-banked register file organization and a selective replacement technique referred as selective register file cache to capture actively reused and short-lived register operands. This alleviates the load on register file while performing read and write operations. Thus, the proposed architecture achieved maximum energy saving of 68% while accessing a register file over a conventional embedded processor architecture. Subsequently, it consumes an average energy of 8.48 \(\upmu \)J which is 51% lesser than the energy consumption of reduced-instruction set-computer (RISC-V) baseline processor-architecture.

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Correspondence to Rahul Shrestha.

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Gudaparthi, S., Shrestha, R. Selective register-file cache: an energy saving technique for embedded processor architecture. Des Autom Embed Syst 26, 105–124 (2022). https://doi.org/10.1007/s10617-022-09264-2

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  • DOI: https://doi.org/10.1007/s10617-022-09264-2

Keywords

  • Processor architecture
  • Embedded system and Energy consumption
  • Register file cache
  • Energy saving
  • MiBench benchmark kernels
  • Register file access
  • CMOS process
  • CACTI and SimpleScalar toolsets