A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design

  • Neng Hou
  • Xiaohu Yan
  • Fazhi HeEmail author


In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a research hotspot. As hardware/software co-design is a wide topic, this paper focuses on major developments of three important aspects related to hardware/software partitioning, which has great effects on the performance of embedded systems. Firstly, various partitioning models including hardware architectures and abstract models are surveyed. Secondly, classical and new algorithms for hardware/software partitioning are classified and analyzed. Thirdly, existing parallel algorithms for hardware/software co-design are discussed in details. Finally, possible research directions are pointed out in conclusion.


Hardware/software co-design Hardware/software partitioning Partition model Solution algorithm Algorithm parallelization 



Funding was provided by National Natural Science Foundation of China (Grant No. 61472289) and National Key Research and Development Project (Grant No. 2016YFC0106305).


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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.School of Computer ScienceWuhan UniversityWuhanChina

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