FPGA implementation of an optimized key expansion module of AES algorithm for secure transmission of personal ECG signals

Abstract

Advanced Encryption Standard was published as Federal Information Processing Standard by National Institute of Standards and Technology in 2001. AES is a symmetric non fiestel block cipher cryptographic algorithm that encrypts and decrypts the data block of 128 bits using different key sizes (128, 192, 256). Based on the block sizes, the number of rounds of encryption and decryption operations and the number of subkeys generated from the main key differs. In this proposed algorithm, the subkey generation architecture is altered to speed up the process of generating the subkeys from the main key. The proposed architecture is simulated and is implemented in FPGA Virtex 5 XC5VLX50T and it is found that the proposed architecture generates all the subkeys by saving 50% of the time taken by architecture proposed in 2001. This paper discusses the implementation of the new proposed algorithm for encryption and decryption process of ECG signals for the purpose of secure communication.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

References

  1. 1.

    National Institute of Standards and Technology (2001) Advanced Encryption Standard (AES). Federal Information Processing Standards Publications—FIPS 197. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf, November 2001

  2. 2.

    Daemen J, Rijmen V (2002) The design of Rijndael. Springer, Berlin

    Book  MATH  Google Scholar 

  3. 3.

    Stallings W (2011) Cryptography and network security, 5th edn. Pearson Education Inc and Dorling Kindersley Publishing Inc, MIT

  4. 4.

    Karthigaikumar P, Rasheed S (2011) Simulation of image encryption using AES algorithm. In: IJCA special issue on “computational science-new dimensions & perspectives” NCCSE, pp 166–172

  5. 5.

    Jarold KN, Karthigaikumar P, Sivamangai NM, Sandhya R, Asok, SB (2013) Hardware implementation of DNA based cryptography. In: 2013 IEEE conference on information & communication technologies (ICT), pp 696–700

  6. 6.

    Chodowiec P, Gaj K (2003) Very compact FPGA implementation of the AES Algorithm. In: Proceedings of cryptographic hardware and embedded system workshop, pp 319–333

  7. 7.

    Chen C-K, Lin C-L, Lin S-L, Chiang C-T (2015) Data encryption and transmission based on personal ECG signals. Int J Sensor Netw Data Commun 4(2):1–13

  8. 8.

    Reddy SK, Saktivel R, Paneeth P (2011) VLSI implementation of AES crypto processor for high throughput. Int J Adv Eng Sci Technol 6(1):22–26

  9. 9.

    Mangard S (2002) A simple power-analysis (SPA) attack on implementations of the AES key expansion. Inf Secur Cryptol 2587(1):343–358

  10. 10.

    Chen C-N, Yen S-M (2003) Differential fault analysis on AES key schedule and some countermeasures. Inf Secu Priv 2727(1):118–129

  11. 11.

    Hammad I, El-Sankary K, El-Masry E (2012) High speed AES encryptor with efficient merging techniques. IEEE Embed Syst Lett 2(3):67–71

  12. 12.

    Yoo SM, Kotturi D, Pan DW, Blizzard J (2005) An AES crypto chip using a high speed parallel pipelined architecture. Microprocess Microsyst 29(1):317–326

  13. 13.

    Jyrwa B, Paily R (2009) An area-throughput efficient FPGA implementation of block cipher AES algorithm. In: International conference on advances in computing, control and telecommunication technologies, 2009, pp 328–332

  14. 14.

    Good T, Benaissa M (2006) Very small FPGA application-specific instruction processor for AES. IEEE Trans Circuits Syst I Regul Pap 53:1477–1486

    Article  Google Scholar 

  15. 15.

    Verbauwhede IM, Schaumont PR, Kuo H (2003) Deign and performance testing of a 2.29 Gb/s Rijndael processor. IEEE J Solid State Circuit 38:569–572

    Article  Google Scholar 

  16. 16.

    Satoh A, Morioka S, Takano K, Munetoh S (2001) A compact Rijndael hardware architecture with S-Box optimization. Springer, Berlin

    Book  MATH  Google Scholar 

  17. 17.

    Karthigaikumar P, Christy NA, Mangai NMS (2015) PSP \({\text{CO}}_{{\text{2 }}}\) : an efficient hardware architecture for AES algorithm for high throughput. Wirel Personal Commun 85(1):305–323

  18. 18.

    Yuhua W, Yanjun L, Yukun Z (2007) FPGA-based implementation and study of AES-128 algorithm. Microcomput Inf 6(1):5–10

  19. 19.

    Christy NA, Karthigaikumar P (2012) FPGA implementation of AES algorithm using composite field arithmetic. In: IEEE International conference devices, circuits and systems, March 2012, pp 713–717

  20. 20.

    Mali M, Novak F, Biasizzo A (2005) Hardware implementation of AES algorithm. J Electr Eng 56(9–10):265–269

    Google Scholar 

  21. 21.

    Mangard S, Aigner M, Moninikus S (2003) A highly regular and scalable AES hardware architecture. IEEE Trans Comput 52(4):483–491

    Article  Google Scholar 

  22. 22.

    Liberatori MC, Bonadero JC (2007) AES—28 Cipher. Minimum area, low cost FPGA implementation. Latin Am Appl Res 37(1):71–77

  23. 23.

    Bulens P, Standaert F-X, Quisquater J-J, Pellegrin P, Rouvroy G (2008) Implementation of the AES-128 on Virtex-5 FPGAs. Supported by Walloon Region, Belgium/First Europe Program

  24. 24.

    Priya SSS, Karthigaikumar P, SivaMangai NM (2015) Generation of 128-Bit blended key for AES algorithm. In: Proceedings of the 49th annual convention of the computer society of India—emerging ICT for Bridging the Future, pp 431–439

  25. 25.

    Lagendijk RL, Erkin Z, Barni M (2013) Encrypted signal processing for privacy protection: conveying the utility of homomorphic encryption and multiparty computation. IEEE Signal Process Mag 30(1):82–105

    Article  Google Scholar 

  26. 26.

    Rahimunnisa K, Karthigaikumar P, Christy N, Kumar S, Jayakumar J (2013) PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC. Eur J Comput Sci 3(4):173–186

  27. 27.

    Jun Y, Jun D, Na L, Yixiong G (2010) FPGA-based design and implementation of reduced AES algorithm. In: International conference on challenges in environmental science and computer engineering, pp 194–198

  28. 28.

    Priya SSS, KarthigaiKumar P, Sivamangai NM, Rejula V (2015) FPGA implementation of efficient AES encryption. In: International conference on innovations in information, embedded and communication systems, pp 1–4

  29. 29.

    Good M, Benaissa M (2005) AES on FPGA from the fastest to the smallest. In: Cryptographic hardware and embedded systems-CHES 2005, International Workshop on Cryptographic Hardware and Embedded Systems. Springer, Berlin, pp 427–440

  30. 30.

    Helion. www.heliontech.com

  31. 31.

    Chena C-K, Lina C-L, Chiangb C-T, Linc S-L (2012) Personalized information encryption using ECG signals with chaotic functions. Inf Sci 193:125–140

    Article  Google Scholar 

  32. 32.

    Anumol TJ, Karthigaikumar P (2011) DWT based invisible image watermarking algorithm for color images. In: IJCA Special Issue on “computational science-new dimensions & perspectives”, pp 76–79

  33. 33.

    Huang J, Lai, Xuejia. (2017) Transposition of AES key schedule. In: 12th China International Conference on Information Security and Cryptology Beijing, China November 4–6, 2016, pp 84–102

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Thanikodi Manoj Kumar.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Manoj Kumar, T., Karthigaikumar, P. FPGA implementation of an optimized key expansion module of AES algorithm for secure transmission of personal ECG signals. Des Autom Embed Syst 22, 13–24 (2018). https://doi.org/10.1007/s10617-017-9189-5

Download citation

Keywords

  • AES
  • FPGA
  • Encryption
  • Decryption
  • Propagation delay
  • Key expansion
  • Electro cardiogram
  • Biomedical