Advertisement

Design Automation for Embedded Systems

, Volume 21, Issue 1, pp 1–36 | Cite as

Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog

  • Muhammad Waseem Anwar
  • Muhammad Rashid
  • Farooque Azam
  • Muhammad Kashif
Article

Abstract

Model Based System Engineering (MBSE) is a renowned approach in the context of embedded systems development. It is frequently used to deal with the structural and behavioral aspects of system design. However, the verification of system design is generally performed in isolation. It is particularly true in the context of assertion based verification. Consequently, there is a huge gap between system design and its verification that seriously effects the productivity and time-to market objectives. Therefore, in this research, we target to reduce this gap by exploiting the features of MBSE and SystemVerilog assertions (SVA’s). This article introduces a novel MBSE approach to model the design verification aspects of embedded systems, along with the system design (structural and behavioral aspects). We propose SystemVerilog in Object Constraint Language (SVOCL), an OCL temporal extension for SystemVerilog, to represent the design verification requirements by means of SVA’s. As a part of research, SVOCL transformation engine has been developed to generate SVA’s code in order to automate the design verification of embedded systems. The application of SVOCL has been validated through four case studies.

Keywords

MBSE SystemVerilog assertions OCL extension Embedded systems SVOCL 

Notes

Acknowledgements

This project is funded by NSTIP (National Science Technology, Innovative Plan), Saudi Arabia under the Technology Area “Information Technology Strategic Priorities” and Track “Software Engineering and Innovated Systems”. We acknowledge the support of KACST (King Abdul-Aziz City for Science and Technology) and STU (Science and Technology Unit) Makkah.

References

  1. 1.
    Andrade E, Maciel P, Callou G, Nogueira B (2009) A methodology for mapping SysML activity diagram to time petri net for requirement validation of embedded real-time systems with energy constraints. In: Third international conference on digital society ICDS, pp 266–271Google Scholar
  2. 2.
    Bazydlo G, Adamski M, Stefanowicz L (2014) Translation UML diagrams into Verilog. In: 7th International conference on human system interactions (HSI), pp 267–271Google Scholar
  3. 3.
    Bengtsson JE, Yi W (2004) Timed automata: semantics, algorithms and tools. In: Desel J, Reisig W, Rozenberg G (eds) ACPN 2003, LNCS, vol 3098. Springer, Heidelberg, pp 87–124Google Scholar
  4. 4.
    Berrani S, Hammad A, Mountassir H (2013) Mapping SysML to modelica to validate wireless sensor networks non-functional requirements. In: 11th International symposium on programming and systems (ISPS), pp 177–186Google Scholar
  5. 5.
    Besnard L, Gautier T, Le Guernic P, Talpin J-P (2010) Compilation of polychronous data flow equations. In: Shukla S, Talpin J-P (eds) Correct-by-construction embedded software synthesis: formal frameworks, methodologies, and tools. Springer, BerlinGoogle Scholar
  6. 6.
    Bilal K, Safouan T (2014) Specification of temporal properties with OCL. Sci Comput Program 96(Part 4):527–551Google Scholar
  7. 7.
    Bill R, Gabmeyer S, Kaufmann P, Seidl M (2014) Model checking of CTL-extended OCL specifications. In: Software language engineering, lecture notes in computer science, vol 8706, pp 221–240Google Scholar
  8. 8.
    Bousse E, Mentre D, Combemale B, Baudry B, Katsuragi T (2012) Aligning SysML with the B method to provide V&V for systems engineering. In: Proceedings of the workshop on model-driven engineering, verification and validation, ACM, pp 11–16Google Scholar
  9. 9.
    Bradfield J, Juliana KF, Perdita S (2002) Enriching OCL using observational Mu-Calculus. In: Fundamental approaches to software engineering lecture notes in computer science, vol 2306, pp 203–217Google Scholar
  10. 10.
    Cengarle MV, Knapp A (2002) Towards OCL/RT. In: FME 2002: formal methods—getting IT right LNCS, vol 2391, pp 390–409Google Scholar
  11. 11.
    Chamai W (2009) Modelica Modeling Language (ModelicaML) a UML profile for modelica, Technical Report 2009:5, EADS IW, Germany, Linkoping University, SwedenGoogle Scholar
  12. 12.
    Conrad S, Turowski K (2001) Temporal OCL: meeting specifications demands for business components. In: Siau K, Halpin T (eds) Unified modeling language: systems analysis, design and development issues. IGI Publishing Hershey, PA, pp 151–165Google Scholar
  13. 13.
    Di Guglielmo G, Di Guglielmo L, Foltinek A, Fujita M, Fummi F, Marconcini C, Pravadelli G (2013) On the integration of model-driven design and dynamic assertion-based verification for embedded software. J Syst Softw 86(8):2013–2033CrossRefGoogle Scholar
  14. 14.
    Distefano D, Katoen JP, Rensink R (2000) On a temporal logic for object-based systems. In: Smith SF, Talcott CL (eds) Formal methods for open object-based distributed systems IV—proceedings of FMOODS’2000. Kluwer Academic Publishers, DordrechtGoogle Scholar
  15. 15.
    Dou W, Bianculli D, Briand L (2014) OCLR: a more expressive, pattern-based temporal extension of OCL. In: Modelling foundations and applications lecture notes in computer science, vol 8569, pp 51–66Google Scholar
  16. 16.
    Dwyer MB, Avrunin GS, Corbett JC (1999) Patterns in property specifications for finite-state verification. In: Proceedings of the 21st international conference on software programming, pp 411–420Google Scholar
  17. 17.
    Ebeid E, Quaglia D, Fummi F (2012) Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification. In: IEEE 15th international symposium on design and diagnostics of electronic circuits and systems (DDECS), pp 187–190. doi: 10.1109/DDECS.2012.6219051
  18. 18.
    Flake S, Mueller W (2002) Real-time systems: specification of properties in UML. In: HICSS proceedings, pp 3977–3986Google Scholar
  19. 19.
    Gamatié A, Le Beux S, Piel É, Ben Atitallah R, Etien A, Marquet P, Dekeyser J-L (2011) A model-driven design framework for massively parallel embedded systems. ACM Trans Embed Comput Syst 10(4) (Article No. 39)Google Scholar
  20. 20.
    Golson S (1993) One-hot state machine design for FPGAs. In: 3rd PLD design conferenceGoogle Scholar
  21. 21.
    IEEE standard for property specification language. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5446004. Accessed Dec 2015
  22. 22.
    IEEE SystemVerilog Standard IEEE STD 1800-2009. http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5354133
  23. 23.
    Iqbal MZ, Arcuri A, Briand L (2013) Environment modeling and simulation for automated testing of soft real-time embedded software. Software and system modeling. Springer, BerlinGoogle Scholar
  24. 24.
    Khan AM, Mallet F, Rashid M (2016) Combining SysML and Marte/CCSL to model complex electronic systems. In: International conference on information systems engineering, April 20–22, Los Angeles, USAGoogle Scholar
  25. 25.
    Knorreck D, Apvrille L (2011) TEPE: a SysML language for time-constrained property modeling and formal verification. ACM SIGSOFT Softw Eng Notes 36(1):1–8. doi: 10.1145/1921532.1921556 CrossRefGoogle Scholar
  26. 26.
    Küster-Filipe J, Stuart A (2006) On a time enriched OCL liveness template. Int J Softw Tools Technol Transfer 8(2):156–166CrossRefGoogle Scholar
  27. 27.
    Launiainen T, Heljanko K, Junttila T (2010) Efficient model checking of PSL safety properties. In: 10th international conference on application of concurrency to system design (ACSD), pp 95–104Google Scholar
  28. 28.
    Lavazza L, Morasca S, Morzenti A (2005) A dual language approach to the development of time-critical systems. Electr Notes Theor Comput Sci 116:227–239CrossRefGoogle Scholar
  29. 29.
    Li L, Coyle FP, Thornton MA (2007) UML to SystemVerilog synthesis for embedded system models with support for assertion generation. In: Proceedings of the ECSI forum on design languagesGoogle Scholar
  30. 30.
    Louati A, Barkaoui K, Jerad C (2015) Temporal properties verification of real-time systems using UML/MARTE/OCL-RT. In: Bouabana-Tebibel T, Rubin S H (eds) Formalisms for reuse and systems integration, advances in intelligent systems and computing, vol 346. Springer International Publishing, Switzerland, pp 133–147Google Scholar
  31. 31.
    Mallet F, Millo J-V, de Simone R (2013) Safe CCSL specifications and marked graphs. In: 11th IEEE/ACM international formal methods and models for codesign (MEMOCODE), pp 157–166Google Scholar
  32. 32.
    Mentor Graphics, QuestaSim. https://www.mentor.com/products/fv/questa/
  33. 33.
    MODEVES Project, SVOCL Transformation. http://www.modeves.com/svoclte.html
  34. 34.
    Mullins J, Oarga R (2007) Model checking of extended OCL constraints on UML models in SOCLe. In: Formal methods for open object-based distributed systems. Lecture notes in computer science, vol 4468, pp 59–75Google Scholar
  35. 35.
    OCL Specifications, version 2.4 2014. http://www.omg.org/spec/OCL/2.4/PDF
  36. 36.
    OMG Object Constraint Language (OCL) Specifications. http://www.omg.org/spec/OCL/
  37. 37.
    Ouchani S, Mohamed OA, Debbabi M (2013) A formal verification framework for BlueSpec SystemVerilog, IEEE proceedings of Forum on Specification & Design Languages (FDL), pp 1–7Google Scholar
  38. 38.
    Quadri IR, Brosse E, Gray I, Matragkas N, Indrusiak LS, Rossi M, Bagnato A, Sadovykh A (2012) MADES FP7 EU project: effective high level SysML/MARTE methodology for real-time and embedded avionics systems. In: 7th International workshop reconfigurable communication-centric systems-on-chip (ReCoSoC), pp 1–8Google Scholar
  39. 39.
    Rashid M, Anwar MW, Amir M (2015) Towards the tools selection in model based system engineering for embedded systems—a systematic literature review. J Syst Softw 106:150–163CrossRefGoogle Scholar
  40. 40.
    Rashid M, Anwar MW, Azam F (2016) Expressing embedded systems verification aspects at higher abstraction level—SystemVerilog in Object Constraint Language (SVOCL). In: 10th IEEE annual systems conference (SysCon)Google Scholar
  41. 41.
    Rashid M, Anwar MW, Azam F, Kashif M (2016) Exploring the platform for expressing SystemVerilog assertions in model based system engineering. In: 7th International conference on information science and applications (ICISA 2016), LNEE, Springer, vol 376, pp 533–544Google Scholar
  42. 42.
    Rashid M, Anwar MW, Azam F, Kashif M (2016) Model-based requirements and properties specification trends for early design verification of embedded systems. In: 11th IEEE system of systems engineering conference (SoSE)Google Scholar
  43. 43.
    Soeken M, Drechsler R (2015) Formal specification level–concepts, methods, and algorithms. Springer, Berlin (e-book)Google Scholar
  44. 44.
    Stancescu S, Neagoe L, Marinescu R, Enoiu EP (2010) A SysML model for code correction and detection systems. In: Proceedings of 33rd MIPRO, pp 189–191Google Scholar
  45. 45.
    Universal Verification Methodology. http://accellera.org/downloads/standards/uvm. Accessed Dec 2015
  46. 46.
    Ziemann P, Gogolla M (2003) OCL extended with temporal logic. In: Perspectives of System Informatics. Lecture Notes on Computer Science, vol 2890, pp 351–357Google Scholar

Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  • Muhammad Waseem Anwar
    • 1
  • Muhammad Rashid
    • 2
  • Farooque Azam
    • 1
  • Muhammad Kashif
    • 3
  1. 1.Department of Computer Engineering, CEMENational University of Sciences and Technology (NUST)IslamabadPakistan
  2. 2.Computer Engineering Department, College of Computer and Information SystemsUmm Al-Qura UniversityMakkahSaudi Arabia
  3. 3.Science and Technology UnitUmm Al-Qura UniversityMakkahSaudi Arabia

Personalised recommendations