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Applying SMT-based verification to hardware/software partitioning in embedded systems

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Abstract

When performing hardware/software co-design for embedded systems, the problem of which functions of the system should be implemented in hardware (HW) or in software (SW) emerges. This problem is known as HW/SW partitioning. Over the last 10 years, a significant research effort has been carried out in this area. In this paper, we present two new approaches to solve the HW/SW partitioning problem by using verification techniques based on satisfiability modulo theories (SMT). We compare the results using the traditional technique of integer linear programming, specifically binary integer programming and a modern method of optimization by genetic algorithm. The experimental results show that SMT-based verification techniques can be effective in particular cases to solve the HW/SW partition problem optimally using a state-of-the-art model checker based on SMT solvers, when compared against traditional techniques.

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Acknowledgments

The authors thank Dr. Z.A. Mann for the contribution with the Part 2 test vectors. The authors also thank the anonymous reviewers for their comments, which helped them to improve the draft version of this paper. This research was supported by CNPq and FAPEAM grants.

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Correspondence to Alessandro B. Trindade.

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Trindade, A.B., Cordeiro, L.C. Applying SMT-based verification to hardware/software partitioning in embedded systems. Des Autom Embed Syst 20, 1–19 (2016). https://doi.org/10.1007/s10617-015-9163-z

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