Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models.
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We chose SCE since the system-level exploration environment is readily available. The concepts are applicable to other SLDE, such as PeaCE.
For the purpose of this paper, we have chosen SpecC  as the SLDL. The principles and concepts, however, are equally transferable to other SLDL, such as SystemC.
Classes are an abstract representation of behaviors and channel .
In the rest of the paper, we will use Behaviors to denote elements in the SLDL. The concept is equivalent to modules or blocks.
Complex signals in Simulink are currently not supported such as non-virtual buses.
A Simulink solver computes the next simulation time with an interval called step size.
SIR is primarily the internal representation of the SpecC SLDL, however producing SystemC have also been shown in .
Algo2Spec currently does not support pipelined execution.
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The work presented in this paper is partially supported by the National Science Foundation under Grant No. 1136027.
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Zhang, J., Schirner, G. Towards closing the specification gap by integrating algorithm-level and system-level design. Des Autom Embed Syst 19, 389–419 (2015). https://doi.org/10.1007/s10617-015-9161-1
- Specification synthesis
- MPSoC design methodology
- Design space exploration
- Algorithm-Architecture co-design