Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

FoRTReSS: a flow for design space exploration of partially reconfigurable systems

  • 235 Accesses

  • 4 Citations


In this paper, we present a flow enabling design space exploration for partially reconfigurable systems with real-time constraints, called FoRTReSS. FoRTReSS allows estimating mixed hardware/software implementations of an application where the hardware design space, the floorplanning of reconfigurable regions placed on the FPGA, is automatically inferred from application resources information, interface constraints and the target device. Real-time constraints are verified by a highly configurable SystemC simulator, RecoSim, handling applications described as control data flow graphs (CDFGs). We demonstrate our approach on an H.264 video decoder and an H.265 encoder targeting the latest Zynq-7000 platforms from Xilinx, embedding a Cortex-A9 dual-core processor. We show that an hardware/software implementation of the H.264 decoder using both processor cores and slice decomposition is possible under real-time constraints, effectively achieving a framerate of 30 frames per second while reducing area requirements compared to a static implementation, using 54 % less slice resources and 44 % less BRAM resources. Additionally we report the ability of the methodology to address very early analysis from high level application specification on the example of an H.265 encoder.

This is a preview of subscription content, log in to check access.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11


  1. 1.

    Xilinx (2012) EPPs: the ideal solution for a wide range of embedded systems

  2. 2.

    Kao C (2005) Benefits of partial reconfiguration. Xcell J 55:65–67

  3. 3.

    Paulsson K, Hübner M, Bayar S, Becker J (2008) Exploitation of run-time partial reconfiguration for dynamic power management in Xilinx Spartan III-based Systems. In: international conference on field programmable logic and applications (FPL), pp 699–700

  4. 4.

    Manet P, Maufroid D, Tosi L, Gailliard G, Mulertt O, Di Ciano M, Legat JD, Aulagnier D, Gamrat C, Liberati R, La Barba V, Cuvelier P, Rousseau B, Gelineau P (2008) An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications. EURASIP J Embed Syst 2008:1:1–1:11

  5. 5.

    Compton K, Hauck S (2002) Reconfigurable computing: a survey of systems and software. ACM Comput Surv 34(2):171–210. doi:10.1145/508352.508353

  6. 6.

    Tessier R, Burleson W (2001) Reconfigurable computing for digital signal processing: a survey. J VLSI Signal Process Syst 28:7–27

  7. 7.

    Duhem F, Muller F, Aubry W, Le Gal B, Ngru D, Lorenzini P (2013) Design space exploration for partially reconfigurable architectures in real-time systems. J Syst Archit (JSA) 59(8), 571–581 (2013). doi:10.1016/j.sysarc.2013.06.007. URL http://www.sciencedirect.com/science/article/pii/S1383762113001215

  8. 8.

    Belaid I, Muller F, Benjemaa M (2010) New three-level resource management enhancing quality of off-line hardware task placement on fpga. EURASIP Int J Reconfig Comput (IJRC)

  9. 9.

    Belaid I, Muller F, Benjemaa M (2011) Static scheduling of periodic hardware tasks with precedence and deadline constraints on reconfigurable hardware devices. EURASIP Int J Reconfig Comput (IJRC), Article ID 591983

  10. 10.

    Bazargan K, Kastner R, Sarrafzadeh M (2000) Fast template placement for reconfigurable computing systems. IEEE Design Test Comput 17(1):68–83. doi:10.1109/54.825678

  11. 11.

    Lodi A, Martello S, Vigo D (1999) Neighborhood search algorithm for the guillotine non-oriented two-dimensional bin packing problem. In: Proceedings of the Meta-Heuristics. Springer, New York, US, pp 125–139

  12. 12.

    Lodi A, Martello S, Vigo D (1999) Heuristic and metaheuristic approaches for a class of two-dimensional bin packing problems. INFORMS J Comput 11(4):345–357

  13. 13.

    Singhal L, Bozorgzadeh E (2007) Multi-layer floorplanning for reconfigurable designs. IET Comput Digital Tech 1(4):276–294

  14. 14.

    Montone A, Santambrogio MD, Redaelli F, Sciuto D (2011) Floorplacement for partial reconfigurable FPGA-based systems. Int J Reconfig Comput 2011:2:1–2:12

  15. 15.

    Vipin K, Fahmy SA (2012) Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration. In: Proceedings of the 8th international symposium on applied reconfigurable computing (ARC), pp 13–25

  16. 16.

    Kumar R, Gordon-Ross A (2011) Formulation-level design space exploration for partially reconfigurable fpgas. In: international conference on field-programmable technology (FPT), pp 1–6

  17. 17.

    Xilinx (2012) Partial Reconfiguration User Guide

  18. 18.

    Sohanghpurwala AA, Athanas P, Frangieh T, Wood A (2011) OpenPR: an open-source partial-reconfiguration toolkit for Xilinx FPGAs. In: IPDPS Workshops. IEEE, pp 228–235

  19. 19.

    Altera (2012) Quartus II Handbook Version 12.1, Vol 1: design and synthesis—design planning for partial reconfiguration

  20. 20.

    Beckhoff C, Koch D, Torresen J (2012) Go ahead: a partial reconfiguration framework. In: Proceedings of the 2012 IEEE 20th international symposium on field-programmable custom computing machines, FCCM ’12 IEEE Computer Society, Washington, DC, USA, pp 37–44

  21. 21.

    Corbetta S, Morandi M, Novati M, Santambrogio MD, Sciuto D, Spoletini P (2009) Internal and external bitstream relocation for partial dynamic reconfiguration. IEEE Trans Very Large Scale Integr Syst 17(11):1650–1654

  22. 22.

    Flynn A, Gordon-Ross A, George AD (2009) Bitstream relocation with local clock domains for partially reconfigurable fpgas. In: Proceedings of the conference on design, automation and test in Europe, DATE ’09. European Design and Automation Association, 3001 Leuven, Belgium, Belgium, pp 300–303

  23. 23.

    Duhem F, Muller F, Lorenzini P (2011) Methodology for designing partially reconfigurable systems using transaction-level modeling. In: conference on design and architectures for signal and image processing (DASIP), pp 316–322

  24. 24.

    Duhem F, Muller F, Lorenzini P (2012) Reconfiguration time overhead on field programmable gate arrays: reduction and cost model. IET Comput Digital Tech 6(2):105–113

  25. 25.

    Foucher C, Muller F, Giulieri A (2012) Fast integration of hardware accelerators for dynamically reconfigurable architecture. In: IEEE CAS 7th international workshop on reconfigurable communication-centric systems-on-chip (ReCoSoC 2012). IEEE, York, UK

  26. 26.

    Jozwik K, Tomiyama H, Honda S, Takada H (2010) A novel mechanism for effective hardware task preemption in dynamically reconfigurable systems. In: FPL’10, pp 352–355

  27. 27.

    Bilavarn S, Khan J, Belleudy C, Bhatti MK (2014) Effectiveness of power strategies for video applications: a practical study. J Real-Time Image Process. doi:10.1007/s11554-013-0394-6. URL http://link.springer.com/article/10.1007/s11554-013-0394-6

  28. 28.

    Muller F (2014) FoRTReSS Toolbox (flow for reconfigurable architecture in real-time systems). https://sites.google.com/site/fortresstoolbox/

  29. 29.

    The Eclipse Foundation (2013) Eclipse graphical modeling framework (GMF). http://www.eclipse.org/modeling/gmp/

  30. 30.

    JDOM Project (2012) JDOM. http://www.jdom.org/

  31. 31.

    x265 Project (2014) x265. http://x265.org/

  32. 32.

    Damak T, Werda I, Bilavarn S, Masmoudi N (2013) Fast prototyping h.264 deblocking filter using esl tools. Trans Syst Signals Devices 8(3):345–362

  33. 33.

    ITU-T (2005) ISO/IEC 14496–10, advanced video coding for generic audiovisual services, ITU-T Recommendation H.264, Version 4

  34. 34.

    D’huys TPKC, Momcilovic S, Pratas F, Sousa L (2014) Reconfigurable data flow engine for hevc motion estimation. In: IEEE international conference on image processing (ICIP)

  35. 35.

    Kalali E, Adibelli Y, Hamzaoglu I (2012) A high performance and low energy intra prediction hardware for high efficiency video coding. In: IEEE 22nd international conference on field programmable logic and applications (FPL 2012)

  36. 36.

    Tiago Dias NR, Sousa L (2014) Unified transform architecture for avc, avs, vc-1 and hevc high-performance codecs. In: EURASIP J Adv Signal Process 2014(1):108

  37. 37.

    ARDMAHN consortium (2013) ARDMAHN project. http://ARDMAHN.org/

Download references


This work was carried out in the framework of project ARDMAHN [37] sponsored by the French National Research Agency under grant ANR-09-SEGI-001, which aims at developing methodologies for home gateways integrating dynamic and partial reconfiguration. This work is also carried out under the BENEFIC project (CA505), a project labelled within the framework of CATRENE, the EUREKA cluster for Application and Technology Research in Europe on NanoElectronics.

Author information

Correspondence to Fabrice Muller.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Duhem, F., Muller, F., Bonamy, R. et al. FoRTReSS: a flow for design space exploration of partially reconfigurable systems. Des Autom Embed Syst 19, 301–326 (2015). https://doi.org/10.1007/s10617-015-9160-2

Download citation


  • Reconfigurable architecture
  • Design space exploration
  • Real-time systems
  • Partial reconfiguration
  • Field programmable gate arrays