Cluster based MPSoC architecture: an on-chip message passing implementation

Abstract

This paper proposes a hardware memory management unit to implement an on-chip message passing protocol for cluster based multi-processors system on chip architectures. Within the architecture each cluster is composed of general purpose processors or digital signal processors, along with a memory. To maintain the coherence of the memory a hardware memory management unit is added in the cluster to increase the performance and support an on-chip message passing communication. The hardware memory management unit has the capacity to allocate, control and limit the access to the memory. In order to show the benefit of our architecture a performance comparison over a classical flat architecture and against a state of the art architecture is driven. The results show an improvement that ranges from 1.2 to 21.77 % over these two architectural models. Finally the hardware cost overhead is studied.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

References

  1. 1.

    Kumar R, Tullsen DM, Jouppi NP (2006) Core architecture optimization for heterogeneous chip multiprocessors. In: Parallel architectures and compilation techniques, pp 23–32

  2. 2.

    Jantsch A, Chen X, Naeem A, Zhang Y, Penolazzi S, Lu Z (2012) Memory architecture and management in an NoC platform. In: Scalable multi-core architectures. Springer, pp 3–31

  3. 3.

    Casu MR, Roch MR, Tota SV, Zamboni M (2011) A NoC-based hybrid message-passing/shared-memory approach to CMP design. Microprocess Microsyst 35(2):261–273

    Article  Google Scholar 

  4. 4.

    Marchesan Almeida G, Sassatelli G, Benoit P, Saint-Jean N, Varyani S, Torres L, Robert M (2009) An adaptive message passing MPSoC framework. Int J Reconfigurable Comput

  5. 5.

    Benini L, Flamand E, Fuin D, Melpignano D (2012) P2012: building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator. In: Design, automation and test in Europe (DATE), pp 983–987

  6. 6.

    http://www.kalray.eu

  7. 7.

    http://www.systematic-paris-region.org/en/projets/teraops

  8. 8.

    Suettlerlein J, Zuckerman S, Gao GR (2013) An implementation of the codelet model. In: International conference on parallel processing, pp 633–644

  9. 9.

    Fiorin L, Lukovic S, Palermo G (2008) Implementation of a reconfigurable data protection module for NoC-based MPSoCs. In: International parallel and distributed processing symposium (IPDPS), pp 1–8

  10. 10.

    Tota S et al (2009) A case study for NoC-based homogeneous MPSoC architectures. Very Large Scale Integr 17(3):384–388. doi:10.1109/TVLSI.2008.2011239

    Article  Google Scholar 

  11. 11.

    Ventroux N, David R (2010) SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications. Next-generation multicore/manycore technologies, pp 6:1–6:12

  12. 12.

    Garibotti R, Ost L, Busseuil R, Adeniyi-Jones C, Sassatelli G, Robert M et al (2013) Simultaneous multithreading support in embedded distributed memory MPSoCs. In: Design automation conference (DAC), ACM, p 83

  13. 13.

    Howard J, Dighe S, Hoskote Y, Vangal S, Finan D, Ruhl G, Jenkins D, Wilson H, Borkar N, Schrom G, Pailet F, Jain S, Jacob T, Yada S, Marella S, Salihundam P, Erraguntla V, Konow M, Riepen M, Droege G, Lindemann J, Gries M, Apel T, Henriss K, Lund-Larsen T, Steibl S, Borkar S, De V, Van der Wijngaart R, Mattson T (2010) A 48-core IA-32 message-passing processor with DVFS in 45 nm CMOS. In: International solid-state circuits conference digest of technical papers (ISSCC), pp 108–109

  14. 14.

    Man C, Bin X, Fuming Q, Qingsong S, Tianzhou C, Like Y (2010) Distributed memory management units architecture for NoC-based CMPs. In: Computer and information technology (CIT), pp 54–61

  15. 15.

    Monchiero M et al (2006) Exploration of distributed shared memory architectures for NoC-based multiprocessors. In: Embedded computer systems: architectures, modeling and simulation (SAMOS), pp 144–151

  16. 16.

    Porquet J et al (2011) NoC-MPU: a secure architecture for flexible co-hosting on shared memory MPSoCs. In: Design, automation and test in Europe (DATE), pp 1–4

  17. 17.

    Qiu X, Dubois M (2005) Moving address translation closer to memory in distributed shared-memory multiprocessors. Parallel Distrib Syst 16(7):612–623

    Article  Google Scholar 

  18. 18.

    Tota SV, Casu MR, Roch MR, Rostagno L, Zamboni M (2010) MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. In: Design, automation test in Europe (DATE), pp 45–50

  19. 19.

    http://www.tilera.com/

  20. 20.

    Bononi L, Concer N (2006) Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. In: Design, automation and test in Europe (DATE), pp 154–159

  21. 21.

    Xie J, Yin S, Ruan X, Ding Z, Tian Y, Majors J, Manzanares A, Qin X (2010) Improving MapReduce performance through data placement in heterogeneous Hadoop clusters. In: International symposium on parallel & distributed processing, workshops and Phd forum (IPDPSW), pp 1–9

  22. 22.

    http://www.ovpworld.org/

  23. 23.

    Lenormand E, Edelin G (2003) An industrial perspective: a pragmatic high end signal processing design environment at Thales. In: Embedded computer systems: architectures, modeling and simulation (SAMOS), pp 52–57

  24. 24.

    http://www.mpi-forum.org/docs/

Download references

Acknowledgments

This research is sponsored by the European Commission under the 7th Framework program within the FlexTiles project (FP7 ICT-288248).

Author information

Affiliations

Authors

Corresponding author

Correspondence to Romain Brillu.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Brillu, R., Pillement, S., Lemonnier, F. et al. Cluster based MPSoC architecture: an on-chip message passing implementation. Des Autom Embed Syst 17, 587–607 (2013). https://doi.org/10.1007/s10617-014-9146-5

Download citation

Keywords

  • MPSoC
  • Cluster
  • Shared memory
  • Distributed memory
  • Hardware memory management unit