Exploration of energy efficient memory organisations for dynamic multimedia applications using system scenarios

Abstract

We propose a memory-aware system scenario approach that exploits variations in memory needs during the lifetime of an application in order to optimize energy usage. Different system scenarios capture the application’s different resource requirements that change dynamically at run-time. In addition to computational resources, the many possible memory platform configurations and data-to-memory assignments are important system scenario parameters. In this work we focus on clustering of different memory requirements into groups and presenting the system scenario generation in detail. The clustering is a non-trivial problem due to the many different memory requirements, which leads to a very large exploration space. An extended memory model is used as a practical enabler, in order to evaluate the methodology. The memory models include existing state-of-the-art memories, available from industry and academia, and we show how they are employed during the system design exploration phase. Both commercial SRAM and standard cell based memory models are explored in this study. The effectiveness of the proposed methodology is demonstrated and tested using a large set of multimedia benchmarks published in the Polybench, Mibench and Mediabench suites, representative for the domain of multimedia applications. Reduction in energy consumption in the memory subsystem ranges from 35 to 55 % for the chosen set of benchmarks.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

References

  1. 1.

    Abraham SG, Mahlke SA (1999) Automatic and efficient evaluation of memory hierarchies for embedded systems. In: Proceedings of the microarchitecture, 1999. MICRO-32. 32nd annual international symposium on, IEEE, pp 114–125

  2. 2.

    Benini L et al (2000) Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation. IEEE Design Test Comput 17(2):74–85. doi:10.1109/54.844336

    Article  Google Scholar 

  3. 3.

    Benini L, Macii A, Poncino M (2000) A recursive algorithm for low-power memory partitioning. In: Proceedings of the 2000 international symposium on low power electronics and design, pp 78–83

  4. 4.

    Binkert N et al (2011) The gem5 simulator. SIGARCH Comput Archit News 39(2):1–7

    Article  Google Scholar 

  5. 5.

    Chen S, Postula A (2000) Synthesis of custom interleaved memory systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 8(1):74–83

    Article  Google Scholar 

  6. 6.

    Chen F, Sha EHM (1999) Loop scheduling and partitions for hiding memory latencies. In: Proceedings of the 12th international symposium on System synthesis. IEEE Computer Society, p 64

  7. 7.

    Cheung E et al (2009) Memory subsystem simulation in software tlm/t models. Proc Asia South Pac Design Autom Conf 2009:811–816. doi:10.1109/ASPDAC.2009.4796580

    Google Scholar 

  8. 8.

    Chung EY et al (2002) Contents provider-assisted dynamic voltage scaling for low energy multimedia applications. In: Proceedings of the 2002 international symposium on low power electronics and design, ISLPED ’02, pp 42–47

  9. 9.

    Filippopoulos I et al (2012) Memory-aware system scenario approach energy impact. NORCHIP 2012:1–6. doi:10.1109/NORCHP.2012.6403111

    Google Scholar 

  10. 10.

    Garcia P et al (2006) An overview of reconfigurable hardware in embedded systems. EURASIP J Embed Syst 2006(1):13–13

    Article  Google Scholar 

  11. 11.

    Gheorghita SV et al (2009) System-scenario-based design of dynamic embedded systems. ACM Trans Des Autom Electron Syst 14(1):3:1–3:45

    Article  Google Scholar 

  12. 12.

    Gonzalez R, Horowitz M (1996) Energy dissipation in general purpose microprocessors. IEEE J Solid-State Circuits 31(9):1277–1284. doi:10.1109/4.535411

    Article  Google Scholar 

  13. 13.

    Grun P, Dutt N, Nicolau A (2000) Mist: An algorithm for memory miss traffic management. In: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design. IEEE Press, New York, pp 431–438

  14. 14.

    Guthaus M, Ringenberg J, Ernst D, Austin T, Mudge T, Brown R, (2001) Mibench: a free, commercially representative embedded benchmark suite. In: Workload characterization, 2001. WWC-4. (2001) IEEE on international workshop, pp 3–14

  15. 15.

    Gutierrez JJ, et al. (2008). A case study for generating test cases from use cases. In: Research Challenges in Information Science, 2008. RCIS 2008. Second International Conference on (pp. 209–214). IEEE

  16. 16.

    Hammari E, Catthoor F, Kjeldsberg PG, Huisken J (2010) Application of medium-grain multiprocessor mapping methodology to epileptic seizure predictor. NORCHIP 2010:1–6. doi:10.1109/NORCHIP.2010.5669489

    Google Scholar 

  17. 17.

    Hammari E, Catthoor F, Kjeldsberg PG, Huisken J, Tsakalis K, Iasemidis L (2012) Realization of dynamical electronic systems. In: The international conference on engineering of reconfigurable systems and algorithms

  18. 18.

    Himpe S et al. (2002) MTG* and grey-box: modeling dynamic multimedia applications with concurrency and non-determinism. In: System specification and design languages: best of FDL02

  19. 19.

    Hulzink J et al (2011) An ultra low energy biomedical signal processing system operating at near-threshold. IEEE Trans Biomed Circuits Sys 5(6):546–554

    Article  Google Scholar 

  20. 20.

    Jacob BL, Chen PM, Silverman SR, Mudge TN (1996) An analytical model for designing memory hierarchies. IEEE Trans Comput 45(10):1180–1194

    Article  MATH  Google Scholar 

  21. 21.

    Jantsch A, Ellervee P, Hemani A, Öberg J, Tenhunen H (1994) Hardware/software partitioning and minimizing memory interface traffic. In: Proceedings of the conference on European design automation. IEEE Computer Society Press, pp 226–231

  22. 22.

    Kandemir M, Sezer U, Delaluz V (2001) Improving memory energy using access pattern classification. In: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, IEEE Press, pp 201–206

  23. 23.

    Kritikakou A et al (2014) A scalable and near-optimal representation for storage size management. In: ACM transaction architecture and code optimization. 11(1):1–25. doi:10.1145/2579677

  24. 24.

    Kritikakou A et al (2013) Near-optimal & scalable intra-signal in-place for non-overlapping & irregular access scheme. In: ACM transaction on design automation of electronic systems (TODAES) ACM, New York, NY

  25. 25.

    Lee C et al (1997) Mediabench: a tool for evaluating and synthesizing multimedia and communicatons systems. In: Proceedings of the 30th annual ACM/IEEE international symposium on microarchitecture. IEEE Computer Society, pp 330–335

  26. 26.

    Li Y, Wolf WH (1999) Hardware/software co-synthesis with memory hierarchies. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 18(10):1405–1417

    Article  Google Scholar 

  27. 27.

    Ma Z et al (2007) Systematic methodology for real-time cost-effective mapping of dynamic concurrent task-based systems on heterogenous platforms, 1st edn. Springer, Berlin

    Book  Google Scholar 

  28. 28.

    Macii A, Benini L, Poncino M (2002) Memory design techniques for low-energy embedded systems. Kluwer Academic Publishers, Dordrecht

    Book  MATH  Google Scholar 

  29. 29.

    Marchal P, et al (2003) SDRAM energy-aware memory allocation for dynamic multi-media applications on multi-processor platforms. In: DATE, pp 516–521

  30. 30.

    Meinerzhagen P et al (2011) Benchmarking of standard-cell based memories in the sub-vt domain in 65-nm cmos technology. IEEE Trans Emerg Selected Topics Circuits Syst 1(2)

  31. 31.

    Meinerzhagen P, Roth C, Burg A (2010) Towards generic low-power area-efficient standard cell based memory architectures. In: IEEE international midwest symposium oncircuits and systems (MWSCAS), 2010 53rd. IEEE Press, , New York, pp 129–132

  32. 32.

    Miniskar NR (2012) System scenario based resource management of processing elements on mpsoc. PhD thesis, Katholieke Universiteit Leuven

  33. 33.

    Oshima Y, Sheu BJ, Jen SH (1997) High-speed memory architectures for multimedia applications. Circuits and Devices Magazine, IEEE 13(1):8–13

    Article  Google Scholar 

  34. 34.

    Palkovic M et al (2006) Systematic preprocessing of data dependent constructs for embedded systems. J Low Power Electron (2)1

  35. 35.

    Palkovic M, Catthoor F, Corporaal H (2006) Dealing with variable trip count loops in system level exploration. In: Proceedings of the 4th workshop on optimizations for DSP and embedded systems. IEEE and ACM SIGMICRO, pp 21–30

  36. 36.

    Palkovic M, Corporaal H, Catthoor F (2007) Heuristics for scenario creation to enable general loop transformations. In: 2007 international symposium on system-on-chip, pp 1–4

  37. 37.

    Panda PR et al (2001) Data and memory optimization techniques for embedded systems. ACM Trans Des Autom Electron Syst 6(2):149–206

    Article  MathSciNet  Google Scholar 

  38. 38.

    Passes N, Sha EM, Chao LF (1995) Multi-dimensional interleaving for time-and-memory design optimization. In: Proceedings of the Computer Design: VLSI in Computers and Processors, 1995. ICCD’95, 1995 IEEE International Conference on, IEEE, pp 440–445

  39. 39.

    Pouchet L (2012) Polybench: the polyhedral benchmark suite. http://www.cs.ucla.edu/~pouchet/software/polybench/

  40. 40.

    Ryser HJ (1963) Combinatorial mathematics. McGraw-Hill, New York

  41. 41.

    Schmit H, Thomas DE (1997) Synthesis of application-specific memory designs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5(1):101–111

  42. 42.

    Simunic T et al (1999) Cycle-accurate simulation of energy consumption in embedded systems. In: Proceedings of the 36th design automation conference, 1999, pp 867–872

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Iason Filippopoulos.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Filippopoulos, I., Catthoor, F. & Kjeldsberg, P.G. Exploration of energy efficient memory organisations for dynamic multimedia applications using system scenarios. Des Autom Embed Syst 17, 669–692 (2013). https://doi.org/10.1007/s10617-014-9145-6

Download citation

Keywords

  • System scenarios
  • Design space exploration
  • Reconfigurable design
  • Memory reconfiguration
  • Dynamic multimedia applications