RIDER: Ring deflection router with buffers

Abstract

The network-on-chip is becoming an increasingly important component of chip multiprocessors. Recently bufferless deflection routers were proposed, aiming to reduce hardware cost in comparison to classic virtual channel based routers, by eliminating router buffers. We propose RIDER, a low cost deflection router based on an internal rotating ring structure with minimal number of buffers. We compare RIDER with 16 buffers to a wormhole router with 12 buffers, a virtual channel buffered router with 64 buffers, to CHIPPER, a bufferless deflection router with no buffers, and to MinBD, a buffered deflection router with four buffers.

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References

  1. 1.

    Carlson TE, Heirman W, Eeckhout L (2011) SNIPER: exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In: International conference for high performance computing, networking, storage and analysis, p 52

  2. 2.

    Fallin C, Craik C, Mutlu O (2011) CHIPPER: a low-complexity bufferless deflection router. In: 17th international symposium on high performance computer, architecture, pp 144–155

  3. 3.

    Fallin C, Nazario G, Yu X, Chang K, Ausavarungnirun R, Mutlu O (2012) MinBD: Minimally-buffered deflection routing for energy-efficient interconnect. In: Sixth international symposium on networks-on-chip, pp 1–10

  4. 4.

    Howard J, Dighe S, Vangal SR, Ruhl G, Borkar N, Jain S, Erraguntla V, Konow M, Riepen M, Gries M et al (2011) A 48-core ia-32 processor in 45 nm cmos using on-die message-passing and dvfs for performance and power scaling. IEEE J Solid State Circuits 46(1):173–183

    Article  Google Scholar 

  5. 5.

    Jiang N, Becker DU, Michelogiannakis G, Balfour J, Towles B, Shaw D, Kim J, Dally W (2013) A detailed and flexible cycle-accurate network-on-chip simulator. In: IEEE international symposium on performance analysis of systems and software (ISPASS), pp 86–96

  6. 6.

    Jose J, Nayak B, Kumar K, Mutyam M (2013) DeBAR: deflection based adaptive router with minimal buffering. In: Conference on design, automation and test in, Europe, pp 1583–1588

  7. 7.

    Kodi AK, Sarathy A, Louri A (2008) iDEAL: Inter-router dual-function energy and area-efficient links for network-on-chip (NoC) architectures. ACM SIGARCH Comput Archit News 36:241–250

    Article  Google Scholar 

  8. 8.

    Konstantinidou S, Snyder L (1994) The chaos router. IEEE Trans Comput 43(12):1386–1397

    Article  Google Scholar 

  9. 9.

    Kumar A, Peh LS, Kundu P, Jha NK (2007) Express virtual channels: towards the ideal interconnection fabric. ACM SIGARCH Comput Archit News 35:150–161

    Article  Google Scholar 

  10. 10.

    Kumary A, Kunduz P, Singhx A, Pehy LS, Jhay N (2007) A 4.6 tbits/s 3.6 ghz single-cycle noc router with a novel switch allocator in 65nm cmos. In: 25th international conference on computer design, pp 63–70

  11. 11.

    Lu Z, Zhong M, Jantsch A (2006) Evaluation of on-chip networks using deflection routing. In: 16th ACM great lakes symposium on VLSI, pp 296–301

  12. 12.

    Michelogiannakis G, Sanchez D, Dally WJ, Kozyrakis C (2010) Evaluating bufferless flow control for on-chip networks. In: Fourth international symposium on networks-on-chip, pp 9–16

  13. 13.

    Moscibroda T, Mutlu O (2009) A case for bufferless routing in on-chip networks. ACM SIGARCH Comput Archit News 37(3):196–207

    Article  Google Scholar 

  14. 14.

    Mullins R, West A, Moore S (2004) Low-latency virtual-channel routers for on-chip networks. ACM SIGARCH Comput Archit News 32(2):188

    Article  Google Scholar 

  15. 15.

    Nicopoulos CA, Park D, Kim J, Vijaykrishnan N, Yousif MS, Das CR (2006) Vichar: a dynamic virtual channel regulator for network-on-chip routers. In: 39th annual international symposium on microarchitecture, pp 333–346

  16. 16.

    Oxman G, Weiss S, Birk YT (2012) Buffered deflection routing for networks-on-chip. In: Interconnection network architecture: on-chip, multi-chip, workshop, pp 9–12

  17. 17.

    Peh LS, Dally WJ (2001) A delay model for router microarchitectures. IEEE Micro 21(1):26–34

    Article  Google Scholar 

  18. 18.

    Ramanujam RS, Soteriou V, Lin B, Peh LS (2010) Design of a high-throughput distributed shared-buffer NoC router. In: Fourth international symposium on networks-on-chip, pp 69–78

  19. 19.

    Sun C, Chen CHO, Kurian G, Wei L, Miller J, Agarwal A, Peh LS, Stojanovic V (2012) DSENT-A tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In: Sixth international symposium on networks-on-chip, pp 201–210

  20. 20.

    Woo SC, Ohara M, Torrie E, Singh JP, Gupta A (1995) The SPLASH-2 programs: characterization and methodological considerations. ACM SIGARCH Comput Archit News 23(2):24–36

    Article  Google Scholar 

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Correspondence to Gadi Oxman.

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Oxman, G., Weiss, S. RIDER: Ring deflection router with buffers. Des Autom Embed Syst 18, 141–155 (2014). https://doi.org/10.1007/s10617-014-9130-0

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Keywords

  • NoC
  • Router architecture
  • Deflection routing