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Tucan

Virtual prototype generation and time constraints analysis of real-time embedded systems

Abstract

This paper presents Tucan, an approach to automatically create a virtual prototype (VP) and to support the analysis of VP testing results to validate time constraint requirements in real-time embedded systems. Virtual prototyping is a fast and reliable solution to facilitate system testing and time constraint validation. However, analyzing simulation results involves the visual inspection of timing diagrams, which is a time-consuming and complicated task. The complexity of the task grows depending on the number of signals present in a simulation; furthermore, their analysis is prone to errors due to the difficulty in identifying dependencies between the signals created by the system architecture. Our main contributions are: (1) the automatic generation of a high quality VP from a high level specification; (2) the specification of duration constraints, i.e., execution time of components that must be kept within an average time; and (3) duration requirement analysis based on predicted versus obtained behavior. We are able to predict system behavior by building a VP with a behavior model based on Time Petri Nets. We present the advantages of our method through a case study that illustrates the strength of Tucan in helping determine what variations at a specific component level allow the fulfillment of a set of time constraints.

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Notes

  1. 1.

    For example a 16-bit mux can use as much as 100 logic cells depending on the technology and vendor. If each logic cell consists of a Flip-flop and a 4 bit LUT, adding a 16-bit mux to a system can increase the signal count by 400 or more.

  2. 2.

    hiles.uniandes.edu.co.

  3. 3.

    Bell, D., Uml basics: The sequence diagram, http://www.ibm.com/developerworks/rational/library/3101.html (2004).

  4. 4.

    Sequence diagrams in UML 2.0 support the concept of combined fragment to extend the concept of guard, allowing the designer to specify a sets of messages that grouped together show conditional flow in a sequence diagram (conditionals, loops, breaks, etc.). Although messages outside a combined fragment can be assumed to be sequential, we require that they are included inside a sequence fragment.

  5. 5.

    In our case, since all messages are generated within the system it can be assumed that all generated messages are successfully transmitted, thus waiting for a message to be received is equivalent to waiting for it to be sent.

  6. 6.

    There are additional transformation rules for Signals, which vary depending on the Source and Target, which we do not present here for space reasons.

  7. 7.

    Mentor Graphics, System Vision, http://www.mentor.com/products/sm/system_integration_simulation_analysis/systemvision/ (2010).

  8. 8.

    MOHC Ltd, TimingTool, http://www.timingtool.com/.

  9. 9.

    TimingTool, MOHC Ltd, http://www.timingtool.com/, 2009.

  10. 10.

    http://www.realtimeatwork.com/software/sysml-companion/.

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Correspondence to Rubby Casallas.

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Hoyos-Rodríguez, H., Jiménez, F., Casallas, R. et al. Tucan. Des Autom Embed Syst 17, 129–165 (2013). https://doi.org/10.1007/s10617-013-9122-5

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Keywords

  • Real-time embedded systems
  • Design validation
  • Time constraint requirements
  • Time Petri nets