This paper presents Tucan, an approach to automatically create a virtual prototype (VP) and to support the analysis of VP testing results to validate time constraint requirements in real-time embedded systems. Virtual prototyping is a fast and reliable solution to facilitate system testing and time constraint validation. However, analyzing simulation results involves the visual inspection of timing diagrams, which is a time-consuming and complicated task. The complexity of the task grows depending on the number of signals present in a simulation; furthermore, their analysis is prone to errors due to the difficulty in identifying dependencies between the signals created by the system architecture. Our main contributions are: (1) the automatic generation of a high quality VP from a high level specification; (2) the specification of duration constraints, i.e., execution time of components that must be kept within an average time; and (3) duration requirement analysis based on predicted versus obtained behavior. We are able to predict system behavior by building a VP with a behavior model based on Time Petri Nets. We present the advantages of our method through a case study that illustrates the strength of Tucan in helping determine what variations at a specific component level allow the fulfillment of a set of time constraints.
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For example a 16-bit mux can use as much as 100 logic cells depending on the technology and vendor. If each logic cell consists of a Flip-flop and a 4 bit LUT, adding a 16-bit mux to a system can increase the signal count by 400 or more.
Bell, D., Uml basics: The sequence diagram, http://www.ibm.com/developerworks/rational/library/3101.html (2004).
Sequence diagrams in UML 2.0 support the concept of combined fragment to extend the concept of guard, allowing the designer to specify a sets of messages that grouped together show conditional flow in a sequence diagram (conditionals, loops, breaks, etc.). Although messages outside a combined fragment can be assumed to be sequential, we require that they are included inside a sequence fragment.
In our case, since all messages are generated within the system it can be assumed that all generated messages are successfully transmitted, thus waiting for a message to be received is equivalent to waiting for it to be sent.
There are additional transformation rules for Signals, which vary depending on the Source and Target, which we do not present here for space reasons.
Mentor Graphics, System Vision, http://www.mentor.com/products/sm/system_integration_simulation_analysis/systemvision/ (2010).
MOHC Ltd, TimingTool, http://www.timingtool.com/.
TimingTool, MOHC Ltd, http://www.timingtool.com/, 2009.
Andrade E, Maciel P, Callou G, Nogueira B (2009) A methodology for mapping sysml activity diagram to time Petri net for requirement validation of embedded real-time systems with energy constraints. In: Digital Society, 2009. ICDS ’09. Third international conference, pp 266–271
Bernard B, Francois V (2006) Time Petri nets analysis with TINA. In: International conference on quantitative evaluation of systems, pp 123–124
Berthomieu B, Diaz M (1991) Modeling and verification of time dependent systems using time Petri nets. IEEE Trans Softw Eng 17:259–273
Berthomieu B, Menasche M (1983) An enumerative approach for analyzing time Petri nets. In: Proceedings IFIP. Elsevier, Amsterdam, pp 41–46
Bézivin J (2004) In search of a basic principle for model driven engineering, CEPIS, UPGRADE. Eur J Inform Prof 5(2):21–24
Cheng AMK (2002) Real-time systems: scheduling, analysis, and verification, 1st edn. Wiley, New York
Czarnecki K, Helsen S (2006) Feature-based survey of model transformation approaches. IBM Syst J 45(3):621–645. doi:10.1147/sj.453.0621
Andreu D, Bruchon TGN (2004) Traduction automatique d’un réseau de Petri interprété en langage vhdl. Rapport de Recherche 04008, LIRMM, URL http://hal.archives-ouvertes.fr/docs/00/10/91/99/PDF/D309.PDF
De Freitas EP, Wehrmeister MA, Silva ET Jr, Carvalho FC, Pereira CE, Wagner FR (2007) Deraf: a high-level aspects framework for distributed embedded real-time systems design. In: Proceedings of the 10th international conference on early aspects: current challenges and future directions. Springer, Berlin, pp 55–74
Densmore D, Passerone R (2006) A platform-based taxonomy for ESL design. IEEE Des Test Comput 23(5):359–374
Douglass B (2002) Real-time UML. In: Formal techniques in real-time and fault-tolerant systems. Lecture notes in computer science, vol 2469. Springer, Berlin, pp 53–70
Farrar C, Worden K (2007) An introduction to structural health monitoring. Philos Trans R Soc, Math Phys Eng Sci 365(1851):303
Gajski D, Vahid F (1995) Specification and design of embedded hardware-software systems. IEEE Des Test Comput 12(1):53–67
Gherbi A, Khendek F (2006) Uml profiles for real-time systems and their applications. J Object Technol 5:149–169
Giese H, Karsai G, Lee EA, Rumpe B Schätz B (2010) Model-based engineering of embedded real-time systems. Lecture notes in computer science, vol 6100. Springer, Berlin
Gruttner K, Hylla K, Rosinger S, Nebel W (2010) Towards an ESL framework for timing and power aware rapid prototyping of hw/sw systems. In: Forum on specification design languages, IC 2010, pp 1–6
Heineman G, Councill W (2001) Component-based software engineering: putting the pieces together, vol 17. Addison-Wesley, Reading
Hellestrand G (2004) How virtual prototypes aid soc hardware design. http://www.embedded.com/columns/technicalinsights/20300463
Hoyos H, Casallas R, Jiménez F, Correal D (2011) HiLeS2: model driven embedded system virtual prototype generation. In: Proceedings of the 2011 symposium on theory of modeling & simulation: DEVS integrative M&S symposium, Society for Computer Simulation International, TMS-DEVS ’11, pp 75–82
Hoyos H, Casallas R, Jiménez F (2012) HiLeS-T: an ADL for early requirement verification of embedded systems. In: Proceedings of the 5th international workshop on model based architecting and construction of embedded systems, ACES-MB ’12. ACM, New York, pp 7–12
Hoyos H, Casallas R, Jimenez F (2012) Model-based framework for embedded system product line. In: IECON 2012—38th annual conference on IEEE Industrial Electronics Society, pp 3101–3106
Jiménez F (2000) Specification et conception de micro-systemes bases sur des circuits asynchrones. PhD thesis, Institut National des Sciences Appliquees (Toulouse, Fra), LAAS-CNRS (Toulouse, Fra), Uniandes (Bogota, Col)
Kernighan BW, Pike R (1999) The practice of programming. Addison-Wesley, Reading
Kolovos D, Paige R, Polack F (2008) The epsilon transformation language. In: Theory and practice of model transformations, pp 46–60
Martin J (1998) Overview of the EIA 632 standard: processes for engineering a system. In: Digital avionics systems conference, 1998. Proceedings, 17th DASC. The AIAA/IEEE/SAE, vol 1, pp B32–1–9
Martin J (2000) Processes for engineering a system: an overview of the ANSI/EIA 632 standard and its heritage. Syst Eng 3(1):1–26
Merlin P (1974) A study of the recoverability of computer systems. PhD thesis, University Of California, Irvine
Navet N, Merz S (2008) Modeling and verification of real-time systems. Wiley, New York
Sgroi M, Lavagno L, Sangiovanni-Vincentelli A (2000) Formal models for embedded system design. IEEE Des Test Comput 17(2):14–27
Silicon Integration Initiative Inc (1999) Timing diagram markup language. https://www.si2.org/?page=435/tdml/
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Hoyos-Rodríguez, H., Jiménez, F., Casallas, R. et al. Tucan. Des Autom Embed Syst 17, 129–165 (2013). https://doi.org/10.1007/s10617-013-9122-5
- Real-time embedded systems
- Design validation
- Time constraint requirements
- Time Petri nets