Implementation and validation of architectural space exploration techniques for domain-specific reconfigurable computing


Domain specific coarse-grained reconfigurable architectures (CGRAs) have great promise for energy-efficient flexible designs for a suite of applications. Designing such a reconfigurable device for an application domain is very challenging because the needs of different applications must be carefully balanced to achieve the targeted design goals. It requires the evaluation of many potential architectural options to select an optimal solution. Exploring the design space manually would be very time consuming and may not even be feasible for very large designs. Even mapping one algorithm onto a customized architecture can require time ranging from minutes to hours. Running a full power simulation on a complete suite of benchmarks for various architectural options require several days. Finding the optimal point in a design space could require a very long time. We have designed a framework/tool that made such design space exploration (DSE) feasible. The resulting framework allows testing a family of algorithms and architectural options in minutes rather than days and can allow rapid selection of architectural choices. In this paper, we describe our DSE framework for domain specific reconfigurable computing where the needs of the application domain drive the construction of the device architecture. The framework has been developed to automate design space case studies, allowing application developers to explore architectural tradeoffs efficiently and reach solutions quickly. We selected some of the core signal processing benchmarks from the MediaBench benchmark suite and some edge-detection benchmarks from the image processing domain for our case studies. We describe two search algorithms: a stepped search algorithm motivated by our manual design studies and a more traditional gradient based optimization. Approximate energy models are developed in each case to guide the search toward a minimal energy solution. We validate our search results by comparing the architectural solutions selected by our tool to an architecture optimized manually and by performing sensitivity tests to evaluate the ability of our algorithms to find good quality minima in the design space. All selected fabric architectures were synthesized on 130 nm cell-based ASIC fabrication process from IBM. These architectures consume almost same amount of energy on average, but the gradient based approach is more general and promises to extend well to new problem domains. We expect these or similar heuristics and the overall design flow of the system to be useful for a wide range of architectures, including mesh based and other commonly used architectures for CGRAs.

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    We note here that alternatives to this arrangement of dedicated pass gates are possible. In particular, we could provide dedicated routes in conjunction with each ALU to allow that ALU to be bypassed. However, we found such an arrangement to be expensive within the context of our design space, due to the need for additional multiplexers, and we do not consider it here. Instead, we search for the most efficient proportion of dedicated routes to provide, hence keeping the number of additional multiplexers to the minimum that provide us with energy gains vs. energy expense.


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Correspondence to Gayatri Mehta.

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Mehta, G., Jones, A.K. Implementation and validation of architectural space exploration techniques for domain-specific reconfigurable computing. Des Autom Embed Syst 17, 27–51 (2013).

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  • Domain specific reconfigurable computing
  • Coarse-grained reconfigurable architectures
  • Design space exploration