Design Automation for Embedded Systems

, Volume 16, Issue 4, pp 363–380 | Cite as

An efficient Resource Management to optimize the placement of hardware task on FPGA in the RVC framework

  • Manel HentatiEmail author
  • Samya Elaoud
  • Yassine Aoudni
  • Jean-François Nezan
  • Mohamed Abid


Dynamic partial reconfiguration (DPR) functionality allows implementing multi-tasks applications by exchanging tasks in a design at run-time. It is a promising solution to enhance system performances. But, the effective use of DPR is often hampered by the complexity added to the system design process. In this paper, we investigate the implementation of a multi-tasks applications using the DPR in the RVC framework. We present a resource management method which includes three steps: partitioning the application in HW/SW tasks, divided the FPGA in static and dynamic regions and placement the tasks on FPGA. The proposed method is based on using linear programming strategy to find the optimal placement of hardware tasks. We take into account the heterogeneity aspect of the device. The goal is to minimize the resource utilization and fragmentation. We use RVC technology which is based on a specific language for writing dataflow models called RVC-CAL. This language describes the application as set of blocks called actors connected through a network. To test the efficiency of our approach, we exploit the decoder MPEG-4 SP described in RVC-CAL. We measure the quality of placement in terms of tasks rejection, execution time and resource wastage. Application of different data combinations and a comparison with the state-of-the art method show the high performance of the proposed approach.


RVC hardware task Partitioning Placement FPGA Reconfigurable blocks (RBs) Resource optimization Linear programming 


  1. 1.
    Hentati M, Aoundi Y, Nezan JF, Abid M, Deforges O (2011) FPGA dynamic reconfiguration using the RVC technology: inverse quantization case study. In: Conference on design and architectures for signal and image processing (DASIP), Finland, 2011 Google Scholar
  2. 2.
    Kao C (2005) Benefits of partial reconfiguration take advantage of even more capabilities in your FPGA. Xcell J Xilinx I:65–67 Google Scholar
  3. 3.
    Handa M, Vemuri R (2004) Area fragmentation in reconfigurable operating systems. In: Proceedings of the international conference on engineering of reconfigurable systems and algorithms. CSREA, pp 77–83 Google Scholar
  4. 4.
    Mattavelli M, Amer I, Raulet M (2010) The reconfigurable video coding. IEEE Signal Process Mag 27(3):159–167 CrossRefGoogle Scholar
  5. 5.
    Bhattacharyya S, Brebner G, Eker J, Janneck J, Mattavelli M, von Platen C, Raulet M (2008) OpenDF—a dataflow toolset for reconfigurable hardware and multicore systems. In: First Swedish workshop on multi-core computing, MCC, Ronneby, Sweden, November 27–28, 2008, pp 27–28 Google Scholar
  6. 6.
    Gu R, Janneck JW, Bhattacharyya SS, Raulet M, Wipliez M, Plishker W (2009) Exploring the concurrency of an MPEG RVC decoder based on dataflow program analysis. IEEE Trans Circuits Syst Video Technol 19(11):1646–1657 CrossRefGoogle Scholar
  7. 7.
    Janneck IJW, Mattavelli M, Raulet M, Wipliez M (2010) Reconfigurable video coding: a stream programming approach to the specification of new video coding standards. In: Proceedings of the first annual ACM SIGMM conference on multimedia systems MMSys, New York, USA, pp 223–234 CrossRefGoogle Scholar
  8. 8.
    Bazargan K, Kastner R, Sarrafzadeh M (2000) Fast template placement for reconfigurable computing systems. IEEE Des Test Comput 17(1):68–83 CrossRefGoogle Scholar
  9. 9.
    Walder H, Steiger C, Platzner M (2003) Fast online task placement on FPGAs: free space partitioning and 2d-hashing. In: Reconfigurable architectures workshop (RAW), Nice, France, April 2003 Google Scholar
  10. 10.
    Handa M, Vemuri R (2004) An efficient algorithm for finding empty space for on line FPGA placement. In: Design automation conference (DAC), June 2004, pp 960–965 Google Scholar
  11. 11.
    Cui J, Gu Z, Liu W, Deng D (2007) An efficient algorithm for online soft real-time task placement on reconfigurable hardware devices. In: Proceedings of 10th IEEE international symposium on object and component-oriented real-time distributed computing (ISORC). Santorini Island, Greece, May 2007, pp 321–328 CrossRefGoogle Scholar
  12. 12.
    Tomono M, Nakanishi M, Yamashita S, Nakajima Y, Watanabe K (2006) A new approach to online FPGA placement. In: 40th annual conference on information sciences and systems, Princeton, USA, March 2006, pp 145–150 Google Scholar
  13. 13.
    Ahmadinia A, Bednara M, Bobda C, Teich J (2004) A new approach for on-line placement on reconfigurable devices. In: International parallel and distributed processing symposium (IPDPS), Santa Fe, USA, April 2004, pp 1–8 Google Scholar
  14. 14.
    Lu Y, Marconi T, Gaydadjiev G, Bertels K, Meeuws R (2008) A self-adaptive on-line task placement algorithm for partially reconfigurable systems. In: Proceedings of the 22nd annual international parallel and distributed processing symposium (IPDPS 2008)—RAW2008, April 2008 Google Scholar
  15. 15.
    ElGindy H, Middendorf M, Schmeck H, Schmidt B (2000) Task rearrangement on partially reconfigurable FPGAs with restricted buffer. In: Proceedings of the field programmable logic and applications, Vienna, Austria, August 2000, vol 1896, pp 379–388 Google Scholar
  16. 16.
    Marconi T, Lu Y, Bertels KLM, Gaydadjiev GN (2008) Intelligent merging online task placement algorithm for partial reconfigurable systems. In: Proceedings of design, automation and test in Europe 2008 (DATE 08), Munich, Germany, March 2008, pp 1346–1351 CrossRefGoogle Scholar
  17. 17.
    Tabero J, Septtién J, Mecha H, Mozos D (2006) Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. In: Proceedings of the design automation, Yokohama, March 2006, pp 396–401 Google Scholar
  18. 18.
    Danne K, Stühmeier S (2005) Off-line placement of tasks onto reconfigurable hardware considering geometrical task variants. In: From specification to embedded systems application, vol 184. Springer, New York. International federation for information processing CrossRefGoogle Scholar
  19. 19.
    Belaid I, Muller F, Benjemaa M (2010) New three-level resource management enhancing quality of offline hardware task placement on FPGA. Int J Reconfigurable Comput 2010 Google Scholar
  20. 20.
    Walder H, Platzner M (2003) Online scheduling for block-partitioned reconfigurable devices. In: Design, automation and test in Europe (DATE), Munich, Germany, March, pp 290–295 Google Scholar
  21. 21.
    Virtex-5 FPGA configuration user guide, November 2011 Google Scholar
  22. 22.
    Rossi F, Van Beek P (2006) Handbook of constraint programming. Elsevier, Amsterdam, p 157 zbMATHGoogle Scholar
  23. 23.
  24. 24.
    Wipliez M, Roquier G, Nezan J-F (2009) Software code generation for the RVC-CAL language. J Signal Process Syst Google Scholar
  25. 25.
    MPEG video technologies part 4: video tool library. ISO/IEC FDIS 23002-4, 2009 Google Scholar
  26. 26.
    MPEG systems technologies part 4: codec configuration representation. ISO/IEC FDIS 23001-4, 2009 Google Scholar
  27. 27.
    Eker J, Janneck J (2003) CAL language report. ERL technical memo UCB/ERL M03/48 Google Scholar
  28. 28.
    Siret N, Nezan J-F, Rhatay A (2011) Design of a processor optimized for syntax parsing in video decoders. In: Conference on design and architectures for signal and image processing (DASIP), Finland Google Scholar
  29. 29.
    Siret N, Sabry I, Nezan JF, Raulet M (2010) A codesign synthesis from an MPEG-4 decoder dataflow description. In: IEEE international symposium circuit and systems (ISCAS) Google Scholar
  30. 30.
  31. 31.

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Manel Hentati
    • 1
    • 2
    Email author
  • Samya Elaoud
    • 3
  • Yassine Aoudni
    • 2
  • Jean-François Nezan
    • 1
  • Mohamed Abid
    • 2
  1. 1.INSA, IETRUMR 6164RennesFrance
  2. 2.ENIS/CESSfaxTunisia
  3. 3.FSEG/LOGIQSfaxTunisia

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