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Design Automation for Embedded Systems

, Volume 16, Issue 4, pp 339–361 | Cite as

High-level customization framework for application-specific NoC architectures

  • Iraklis AnagnostopoulosEmail author
  • Alexandros Bartzas
  • Iason Filippopoulos
  • Dimitrios Soudris
Article

Abstract

Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5×higher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network’s power consumption by an average of 45 % for both regular and irregular NoC design flow.

Keywords

Network-on-Chip Design methodology Automation framework Mapping Priorities assignment Buffer sizing Regular and irregular topologies 

Notes

Acknowledgements

The authors would like to thank Dionisios Diamantopoulos (NTUA, Greece) for the help he provided regarding the hardware amount of the routers.

References

  1. 1.
    Al Faruque MA, Henkel J (2008) Minimizing virtual channel buffer for routers in on-chip communication architectures. In: Proc of DATE. ACM, New York, pp 1238–1243 Google Scholar
  2. 2.
    Al Faruque MA, Krist R, Henkel J (2008) Adam: run-time agent-based distributed application mapping for on-chip communication. In: Proceedings of the 45th annual design automation conference. ACM, New York Google Scholar
  3. 3.
    Benini L, de Micheli G (2002) Networks on chips: a new SoC. Paradig Comput 35(1):70–78 CrossRefGoogle Scholar
  4. 4.
    Bertozzi D, Jalabert A, Murali S, Tamhankar R, Stergiou S, Benini L, De Micheli G (2005) NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans Parallel Distrib Syst 16(2):113–129 CrossRefGoogle Scholar
  5. 5.
    Bitirgen R et al. (2008) Coordinated management of multiple interacting resources in chip multiprocessors: a machine learning approach. In: Proc of MICRO-41, pp 318–329 Google Scholar
  6. 6.
    Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) Qnoc: Qos architecture and design process for network on chip. J Syst Archit 50(2–3):105–128. Special issue on networks on chip CrossRefGoogle Scholar
  7. 7.
    Bononi L, Concer N (2006) Simulation and analysis of network on chip architectures: ring, spidergon and 2d mesh. In: Proc of DATE, pp 154–159 Google Scholar
  8. 8.
    Borkar S (2007) Thousand core chips: a technology perspective. In: Proc of DAC. ACM, New York, pp 746–749 Google Scholar
  9. 9.
    Cao J et al. (2002) Arms: an agent-based resource management system for grid computing. Sci Program 10:135–148 Google Scholar
  10. 10.
    Carara EA, Calazans NLV, Moraes FG (2009) Managing QoS flows at task level in NoC-Based MPSoCs, p 6. http://www.inf.pucrs.br/~calazans/publications/2009_VLSI_SoC_Carara.pdf
  11. 11.
    Cardoso RS, Kreutz ME, Carro L, Susin AA (2005) Design space exploration on heterogeneous network-on-chip. In: Proc of ISCAS. IEEE Press, New York, pp 428–431 Google Scholar
  12. 12.
    Casavant TL, Kuhl JG (1988) A taxonomy of scheduling in general-purpose distributed computing systems. IEEE Trans Softw Eng 14:141–154 CrossRefGoogle Scholar
  13. 13.
    Chaco: Software for Partitioning Graphs. http://www.cs.sandia.gov/~ bahendr/chaco.html
  14. 14.
    Choudhary N, Gaur M, Laxmi V (2011) Irregular noc simulation framework: irnirgam. In: 2011 international conference on emerging trends in networks and computer communications (ETNCC), pp 1–5 CrossRefGoogle Scholar
  15. 15.
    De Micheli G (2009) An outlook on design technologies for future integrated systems. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(6):777 CrossRefGoogle Scholar
  16. 16.
    Dick RP et al. (1998) Tgff: task graphs for free. In: CODES’98, pp 97–101 Google Scholar
  17. 17.
    Filippopoulos I, Anagnostopoulos I, Bartzas A, Soudris D, Economakos G (2010) Systematic exploration of energy-efficient application-specific network-on-chip architectures. In: Proc of ISVLSI. IEEE Computer Society, Washington, pp 133–138 Google Scholar
  18. 18.
    Goossens K, Dielissen J, Radulescu A (2005) Æhereal network on chip: concepts, architectures, and implementations. IEEE Des Test Comput 22(5):414–421 CrossRefGoogle Scholar
  19. 19.
    Hansson A, Goossens K (2011) A quantitative evaluation of a network on chip design flow for multi-core consumer multimedia applications. Des Autom Embed Syst 15:159–190. doi: 10.1007/s10617-011-9073-7 CrossRefGoogle Scholar
  20. 20.
    Hendrickson B, Leland R (1995) A multilevel algorithm for partitioning graphs. In: Proc supercomputing, vol 95, p 285 Google Scholar
  21. 21.
    Howard J et al. (2010) A 48-core ia-32 message-passing processor with dvfs in 45 nm cmos. In: Proc of ISSCC, pp 108–109. doi: 10.1109/ISSCC.2010.5434077 Google Scholar
  22. 22.
    Hu J, Marculescu R (2004) Application-specific buffer space allocation for networks-on-chip router design. In: Proc of ICCAD. IEEE Computer Society, Washington, pp 354–361 Google Scholar
  23. 23.
    Hu J, Marculescu R (2005) Energy- and performance-aware mapping for regular noc architectures. IEEE Trans Comput-Aided Des Integr Circuits Syst 24(4):551–562 CrossRefGoogle Scholar
  24. 24.
    Jantsch A, Tenhunen H (eds) (2003) Networks on chip. Kluwer Academic, Dordrecht Google Scholar
  25. 25.
    Kobbe S et al. (2011) Distrm: distributed resource management for on-chip many-core systems. In: Proc of CODES+ISSS, pp 119–128 Google Scholar
  26. 26.
    Lai K et al. (2005) Tycoon: an implementation of a distributed, market-based resource allocation system. Multiagent Grid Syst 1:169–182 zbMATHGoogle Scholar
  27. 27.
    Lecler JJ, Baillieu G (2011) Application driven network-on-chip architecture exploration & refinement for a complex soc. Des Autom Embed Syst 15:133–158. doi: 10.1007/s10617-011-9075-5 CrossRefGoogle Scholar
  28. 28.
    Lee HG, Ogras UY, Marculescu R, Chang N (2006) Design space exploration and prototyping for on-chip multimedia applications. In: Proc of DAC. ACM, New York, pp 137–142 Google Scholar
  29. 29.
    Murali S, De Micheli G (2004) Sunmap: a tool for automatic topology selection and generation for nocs. In: Proc of DAC. ACM, New York, pp 914–919 Google Scholar
  30. 30.
    Murali S, Micheli GD (2004) Bandwidth-constrained mapping of cores onto NoC architectures. In: Proc of DATE. IEEE Computer Society, Washington, p 20896 Google Scholar
  31. 31.
    Nesbit K et al. (2008) Multicore resource management. IEEE MICRO 28(3):6–16 CrossRefGoogle Scholar
  32. 32.
  33. 33.
    Noxim: network-on-chip simulator. http://sourceforge.net/projects/noxim/
  34. 34.
    Ogras U, Marculescu R (2005) Application-specific network-on-chip architecture customization via long-range link insertion. In: Proc of ICCAD, pp 246–253 Google Scholar
  35. 35.
    Rajkumar R et al. (1997) A resource allocation model for qos management. In: Proc of RTSS, pp 298–307 Google Scholar
  36. 36.
    Seiler L et al. (2008) Larrabee: a many-core x86 architecture for visual computing. ACM Trans Graph 27:18:1–18:15 CrossRefGoogle Scholar
  37. 37.
    Semiconductor Industry Association: International technology roadmap for semiconductors (2006). http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm
  38. 38.
    Shang L, Peh LS, Jha NK (2003) Powerherd: dynamic satisfaction of peak power constraints in interconnection networks. In: Proc of ICS. ACM, New York, pp 98–108 Google Scholar
  39. 39.
  40. 40.
    STMicroelectronics (2005) STNoC: building a new system-on-chip paradigm. White Paper Google Scholar
  41. 41.
    van Berkel CHK (2009) Multi-core for mobile phones. In: Proc of DATE. EDAA, Leuven, pp 1260–1265 Google Scholar
  42. 42.
    Vangal S, Howard J, Ruhl G, Dighe S, Wilson H, Tschanz J, Finan D, Iyer P, Singh A, Jacob T et al. (2007) An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS. In: Proc of ISSCC. IEEE Press, New York, pp 98–589 Google Scholar
  43. 43.
    Ye TT, Benini L, De Micheli G (2003) Packetized on-chip interconnect communication analysis for mpsoc. In: Proceedings of the conference on design, automation and test in Europe, vol 1 Google Scholar
  44. 44.
    Zhang W, Li T (2008) Managing multi-core soft-error reliability through utility-driven cross domain optimization. In: Proc of ASAP Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Iraklis Anagnostopoulos
    • 1
    Email author
  • Alexandros Bartzas
    • 1
  • Iason Filippopoulos
    • 2
  • Dimitrios Soudris
    • 1
  1. 1.School of Electrical and Computer EngineeringNational Technical University of Athens (NTUA)AthensGreece
  2. 2.Department of Electronics and TelecommunicationsNorwegian University of Science and Technology (NTNU)TrondheimNorway

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