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Design Automation for Embedded Systems

, Volume 16, Issue 4, pp 293–317 | Cite as

Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC

  • Young-Pyo Joo
  • Sungchan KimEmail author
  • Soonhoi Ha
Article

Abstract

Multiprocessor System-on-Chip (MPSoC) systems are evolving towards a processor pool-based architecture that employs hierarchical on-chip networks for inter- and intra-processor pool communication. Since the design space of processor pool-based MPSoCs is extremely wide, the application-specific optimization of on-chip communication architecture is a nontrivial task. This paper presents a systematic methodology for a cascaded bus matrix-based on-chip network design for processor pool-based MPSoCs. Our approach finds sub-optimal architectures in terms of energy consumption and on-chip area while satisfying given performance constraints. The proposed approach allows for independent configurations of processor pools, which leads to better solutions than seen in previous work. Since a simulation is too time-consuming to evaluate the performance of complex on-chip networks, we propose to prune the designs space efficiently by two static analysis techniques to minimize the use of simulations. Thanks to the static analysis techniques, our approach achieves an order of magnitude speed improvement for architecture exploration without performance loss, compared with simulation-based approaches.

Keywords

Multiprocessor Processor-pool On-chip hierarchical bus matrix Architecture exploration Evolutionary algorithm 

Notes

Acknowledgements

This research was supported by Center for Advanced Image and Information Technology, Chonbuk National University, and research funds of Chonbuk National University in 2011, and Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0023325). This research was partly supported by the MKE (The Ministry of Knowledge Economy), Korea, under the ITRC (Information Technology Research Center) support program supervised by the NIPA (National IT Industry Promotion Agency) (NIPA-2013-H0301-13-1011).

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Samsung ElectronicsGyeonggiKorea
  2. 2.Division of Computer Science and EngineeringChonbuk National UniversityJeonjuKorea
  3. 3.School of Computer Science and EngineeringSeoul National UniversitySeoulKorea

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