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Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marte

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Abstract

Process networks and data-flow graphs are used to capture data-dependencies in computation-intensive embedded systems. Their simplicity allows the computation of static schedules that reduce the dynamic overhead and increase predictability. The resulting schedule is a total ordering of actor computations and communications. It can therefore become an over-specification of the initial system when several schedules are valid. This is particularly the case for multidimensional data-flow applications.

We propose a methodology to avoid such an over-specification. We propose to use logical time to capture explicitly all the valid schedules for a given multi-dimensional data-flow model. Then, we show that the proposed approach allows for a progressive and explicit refinement of computation scheduling that also captures constraints imposed by the environment and the execution platform. All this is achieved by using uml marte concepts and the resulting models can be considered for simulation and analysis with existing tools for early design validation. The whole approach is validated on a typical application devoted to radar signal processing.

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Notes

  1. http://timesquare.inria.fr/.

  2. The instance of the repeated part whose coordinate into the repetition space is 0 on each dimension.

  3. The shape of a port gives the size of the matrix going through the port.

  4. here again, the keyword shape is used. When it is attached to an elementary task, shape denotes the repetition space.

  5. http://timesquare.inria.fr.

  6. http://www.papyrusuml.org.

  7. Let us note that we do not model here the failed attempts to capture the resource but only the successful ones.

  8. Throughout this last section, figures are screen captures of actual uml models.

  9. http://timesquare.inria.fr.

  10. This red rectangle has been superimposed for the discussion. timesquare can only display groups of ticks of the same clock (in green).

References

  1. Abdallah A, Gamatié A, Dekeyser JL (2010) Correct and energy-efficient design of socs: the h.264 encoder case study. In: 2010 international symposium on system on chip (SoC), pp 115–120

    Chapter  Google Scholar 

  2. Alfaro L, Henzinger TA (2001) Interface theories for component-based design. In: Henzinger TA, Kirsch CM (eds) Embedded software. Lecture notes in computer science, vol 2211. Springer, Berlin, Heidelberg, pp 148–165

    Chapter  Google Scholar 

  3. André C (2009) Syntax and semantics of the Clock Constraint Specification Language (CCSL). Research Report 6925, INRIA. http://hal.inria.fr/inria-00384077/

  4. Benveniste A, Le Guernic P, Jacquemot C (1991) Synchronous programming with events and relations: the SIGNAL language and its semantics. Sci Comput Program 16(2):103–149

    Article  MathSciNet  MATH  Google Scholar 

  5. Berry G (2000) The foundations of esterel. Proof, language and interaction: essays in honour of Robin Milner, pp 425–454

  6. Boulet P, Marquet P, Piel E, Taillard J (2007) Repetitive allocation modeling with MARTE. In: Forum on specification and design languages (FDL’07), Barcelona, Spain

    Google Scholar 

  7. Boussinot F, De Simone R (2002) The ESTEREL language. Proc IEEE 79(9):1293–1304

    Article  Google Scholar 

  8. Dumont P (2005) Spécification multidimensionnelle pour le traitement du signal systématique. Ph.D. thesis

  9. Falk J, Keinert J, Haubelt C, Teich J, Zebelein C (2010) Integrated modeling using finite state machines and dataflow graphs. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J (eds) Handbook of signal processing systems. Springer, New York, pp 1041–1075. http://dx.doi.org/10.1007/978-1-4419-6345-1_36

    Chapter  Google Scholar 

  10. Feautrier P (1996) Automatic parallelization in the polytope model. In: Perrin GR, Darte A (eds) The data parallel programming model. Lecture notes in computer science, vol 1132. Springer, Berlin/Heidelberg, pp 79–103

    Chapter  Google Scholar 

  11. Fidge C (2002) Logical time in distributed computing systems. Computer 24(8):28–33

    Article  Google Scholar 

  12. Peraldi Frati MA, Deantoni J (2011) Scheduling multi clock real time systems: from requirements to implementation. In: IEEE int symp on object/component/service-oriented real-time distributed computing. IEEE Computer Society, Washington, pp 50–57

    Chapter  Google Scholar 

  13. Gamatié A (2011) Specification of data intensive applications with data dependency and abstract clocks. In: Furht B, Escalante A (eds) Handbook of data intensive computing. Springer, New York, pp 323–348. http://dx.doi.org/10.1007/978-1-4614-1415-5_12

    Chapter  Google Scholar 

  14. Gamatié A, Beux SL, Piel É., Atitallah RB, Etien A, Marquet P, Dekeyser JL (2011) A model-driven design framework for massively parallel embedded systems. ACM Trans Embed Comput Syst 10(4):39

    Article  Google Scholar 

  15. Gascon R, Mallet F, DeAntoni J (2011) Logical time and temporal logics: comparing UML MARTE/CCSL and PSL. In: Combi C, Leucker M, Wolter F (eds) 18th int. symp. on temporal representation and reasoning, TIME, Lübeck, Germany. IEEE Press, Los Alamitos, pp 141–148

    Google Scholar 

  16. Glitia C (2009) Optimisation des applications de traitement systématique intensives sur systems-on-chip. Ph.D. thesis, Université Lille 1, Sciences et Technologies

  17. Glitia C, Boulet P (2008) High level loop transformations for multidimensional signal processing embedded applications. In: SAMOS 2008 workshop, Samos, Greece

    Google Scholar 

  18. Glitia C, Boulet P, Lenormand E, Barreteau M (2011) Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications. J Syst Archit 57(9):815–829

    Article  Google Scholar 

  19. Glitia C, DeAntoni J, Mallet F (2010) Logical time at work: capturing data dependencies and platform constraints. In: Forum on specification and design languages (FDL)

    Google Scholar 

  20. Glitia C, Dumont P, Boulet P (2010) Array-OL with delays, a domain specific specification language for multidimensional intensive signal processing. Multidimens Syst Signal Process 21(2):105–131

    Article  MathSciNet  MATH  Google Scholar 

  21. Kahn G (1974) The semantics of a simple language for parallel programming. In: Rosenfeld JL (ed) Information processing 74. IFIP Congress, pp 471–475. ISBN: 978-072042803-2

    Google Scholar 

  22. Lamport L (1978) Time, clocks, and the ordering of events in a distributed system. Commun ACM 21(7):558–565

    Article  MATH  Google Scholar 

  23. Lee EA (1993) Multidimensional streams rooted in dataflow. In: Architectures and compilation techniques for fine and medium grain parallelism, pp 295–306

    Google Scholar 

  24. Lee EA, Messerschmitt DG (1987) Synchronous data flow. Proc IEEE 75(9):1235–1245

    Article  Google Scholar 

  25. OMG (2009) UML Profile for MARTE, v1.0. Object Management Group. Document number: formal/09-11-02

  26. OMG (2009) UML Superstructure, v2.2. Object Management Group. Formal/2009-02-02

  27. Soula J (2001) Principe de compilation d’un langage de traitement de signal. Ph.D. thesis

  28. Yin L, Mallet F, Liu J (2011) Verification of MARTE/CCSL time requirements in Promela/SPIN. In: 16th IEEE int conf on engineering of complex computer systems, ICECCS, pp 65–74

    Chapter  Google Scholar 

  29. Yu H, Talpin JP, Besnard L, Gautier T, Marchand H, Guernic PL (2011) Polychronous controller synthesis from MARTE CCSL timing specifications. In: Singh S, Jobstmann B, Kishinevsky M, Brandt J (eds) MEMOCODE. IEEE Press, Los Alamitos, pp 21–30

    Google Scholar 

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Authors and Affiliations

  1. INRIA Sophia Antipolis Méditerranée, 06903, Sophia Antipolis, France

    Calin Glitia, Julien DeAntoni, Frédéric Mallet & Jean-Vivien Millo

  2. Université Nice Sophia Antipolis, 06102, Nice, France

    Julien DeAntoni & Frédéric Mallet

  3. I3S, UMR 7271—UNS and CNRS, 06902, Sophia Antipolis, France

    Calin Glitia, Julien DeAntoni, Frédéric Mallet & Jean-Vivien Millo

  4. LIFL, UMR 8022—Univ. Lille 1 and CNRS, 59650, Villeneuve d’Ascq, France

    Pierre Boulet & Abdoulaye Gamatié

  5. INRIA Lille—Nord Europe, 59650, Villeneuve d’Ascq, France

    Pierre Boulet & Abdoulaye Gamatié

  6. Univ. Lille Nord de France, 59650, Villeneuve d’Ascq, France

    Pierre Boulet & Abdoulaye Gamatié

Authors
  1. Calin Glitia
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  2. Julien DeAntoni
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  3. Frédéric Mallet
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  4. Jean-Vivien Millo
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  5. Pierre Boulet
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  6. Abdoulaye Gamatié
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Correspondence to Frédéric Mallet.

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Glitia, C., DeAntoni, J., Mallet, F. et al. Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marte . Des Autom Embed Syst 16, 137–169 (2012). https://doi.org/10.1007/s10617-012-9093-y

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