ASDeX: a formal specification for analog circuit enabling a full automated design validation

Abstract

In this paper an XML based language format to describe specifications of analog IPs and its usage in a validation flow is presented. With the help of an XML-Schema-Definition (XSD) a specification description language called Analog Specification Description in XML (ASDeX) is introduced. An ASDeX-file contains not only specification parameters but also measurement definitions and testbenches to enable specification validation based on simulation. The intention is to generate executable modules (tasks) for running simulations and extracting and checking the actual property values of analog circuits. The task generation is based on a generic template approach using a Meta-Simulator to achieve vendor independent analog IP representation including IP verification.

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Notes

  1. 1.

    LVDS: low-voltage differential signaling.

  2. 2.

    The Essence Framework was a part work of the VISION project (funding label: 01 M 3078). This project is partly supported in accordance with the BMBF “Nanoelectronics” sponsorship scheme within the scope of the Ekompass-sponsorship complex of the Federal Ministry of Education and Research (BMBF).

  3. 3.

    The Meta-Simulator is a PERL software library and developed by Infineon Technologies AG, Germany.

References

  1. 1.

    Alur R, Feder T, Henzinger TA (1996) The benefits of relaxing punctuality. J ACM 43(1):116–146. doi:10.1145/227595.227602

    Article  MATH  MathSciNet  Google Scholar 

  2. 2.

    ASDeX Home (2012) www.em.cs.uni-frankfurt.de/ASDeX

  3. 3.

    Barthel T, Müller D, Pauliuk J (1998) A method for capturing analogue and heterogeneous system specifications. In: Workshop on system design automation (SDA’98), Dresden

    Google Scholar 

  4. 4.

    Bloem R, Galler S, Piterman N, Pnueli A, Weiglhofer M (2007) Automatic hardware synthesis from specifications: a case study. In: Proceedings of the conference on design, automation and test in Europe (DATE’07), April 16–20, 2007

    Google Scholar 

  5. 5.

    Gnucap Home Page (2006) www.gnu.org/software/gnucap/

  6. 6.

    Grimm C, Heupke W, Waldschmidt K (2004) Refinement of mixed-signal systems with affine arithmetic. In: Proceedings of the conference on design, automation and test in Europe (DATE’04), February 16–20, 2004

    Google Scholar 

  7. 7.

    IEEE Standard for IP-XACT (2009) Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows

  8. 8.

    IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI) (1996)

  9. 9.

    Jesser A, Lämmermann S, Pacholik A, Weiss R, Ruf J, Fengler W, Hedrich L, Kropf T, Rosenstiel W (2008) Advanced assertion based design for mixed-signal verification. IEICE Trans Fundam Electron Commun Comput Sci E91-A:3548–3555. Special section on VLSI design and CAD algorithms

    Article  Google Scholar 

  10. 10.

    Kazmierski TJ, Hamid FA (2002) Analogue integrated circuit synthesis from VHDL-AMS behavioural specifications. In: 23rd international conference on microelectronics (MIEL 2002), pp 585–588. doi:10.1109/MIEL.2002.1003325

    Google Scholar 

  11. 11.

    Kruijtzer W, van der Wolf P, de Kock E, Stuyt J, Ecker W, Mayer A, Hustin S, Amerijckx C, de Paoli S, Vaumorin E (2008) Industrial IP integration flows based on IP-XACT™ standards. In: Proceedings of the conference on design, automation and test in Europe (DATE’08), March 10–14, 2008

    Google Scholar 

  12. 12.

    Lämmermann S, Ruf J, Kropf T, Rosenstiel W, Viehl A, Jesser A, Hedrich L (2010) Towards assertion-based verification of heterogeneous system designs. In: Design, automation test in Europe conference exhibition (DATE), pp 1171–1176

    Google Scholar 

  13. 13.

    Maler O, Nickovic D (2004) Monitoring temporal properties of continuous signals. In: Proceedings of the conference formal modelling and analysis of timed systems (FORMATS), Berlin

    Google Scholar 

  14. 14.

    Maler O, Nickovic D, Pnueli A (2008) Checking temporal properties of discrete, timed and continuous behaviors. In: Avron A, Dershowitz N, Rabinovich A (eds) Pillars of computer science. Lecture notes in computer science, vol 4800. Springer, Berlin/Heidelberg, pp 475–505

    Google Scholar 

  15. 15.

    Mitea O, Meissner M, Hedrich L, Jores P (2011) Automated constraint-driven topology synthesis for analog circuits. In: Proceedings of IEEE/ACM conference on design, automation and test in Europe (DATE’11), March 14–18, 2011

    Google Scholar 

  16. 16.

    Nageldinger U, Esen V, Velten M (2009) Implementierung einer exemplarischen transformation von der beschreibungsmethodik nach Entwurfs-/Dokumentationsdaten. In: Meilensteinbereicht M1.1.3-IFX-Q12, BMBF funding project VISION, August 31, 2009

    Google Scholar 

  17. 17.

    Nickovic D, Maler O (2007) AMT: a property-based monitoring tool for analog systems. In: Proceedings of the conference formal modelling and analysis of timed systems (FORMATS)

    Google Scholar 

  18. 18.

    Steinhorst S, Hedrich L (2008) Model checking of analog systems using an analog specification language. In: Proceedings of the conference on design, automation and test in Europe (DATE’08), March 10–14, 2008. doi:10.1109/DATE.2008.4484700

    Google Scholar 

  19. 19.

    Steinhorst S, Jesser A, Hedrich L (2006) Advanced property specification for model checking of analog systems. In: Proceedings of the analog 2006: 9. ITG/GMM-Fachtagung Entwicklung von Analogschaltungen mit CAE-Methoden

    Google Scholar 

  20. 20.

    Vachoux A, Grimm C, Einwich K (2003) Analog and mixed signal modelling with systemc-ams. In: Proceedings of the 2003 international symposium on circuits and systems, ISCAS’03, vol 3, pp III-914–III-917. doi:10.1109/ISCAS.2003.1205169

    Google Scholar 

  21. 21.

    Vachoux A, Grimm C, Einwich K (2003) Systemc-ams requirements, design objectives and rationale. In: Design, automation and test in Europe conference and exhibition, pp 388–393. doi:10.1109/DATE.2003.1253639

    Google Scholar 

  22. 22.

    www.makotemplates.org (2012) Mako Templates for Python

  23. 23.

    www.w3.org/math (2011) W3C Math Home

  24. 24.

    www.w3schools.com/schema (2012) XML Schema Tutorial

  25. 25.

    Zimmermann J, Bringmann O, Gerlach J, Schaefer F, Nageldinger U (2008) Comprehensive platform and component modeling of heterogeneous interconnected systems. In: Proceedings of the forum on specification and design languages 2008 (FDL’08), September 23–25, 2008

    Google Scholar 

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Correspondence to Mingyu Ma.

Additional information

This work was partly developed within the project SyEnA (project label 01 M 30 86) which is funded within the Research Program ICT 2020 by the German Federal Ministry of Education and Research (BMBF).

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Ma, M., Hedrich, L. & Sporrer, C. ASDeX: a formal specification for analog circuit enabling a full automated design validation. Des Autom Embed Syst 18, 99–118 (2014). https://doi.org/10.1007/s10617-012-9088-8

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Keywords

  • ASDeX
  • Formal specification
  • Analog IPs
  • XML
  • Design flow
  • Validation
  • LVDS
  • OP-AMP
  • A/D converter