HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

Abstract

This paper presents a high level error detection and correction method called HVD code to tolerate multiple bit upsets (MBUs) occurred in memory cells. The proposed method uses parity codes in four directions in a data part to assure the reliability of memories. The proposed method is very powerful in error detection while its error correction coverage is also acceptable considering its low computing latency. HVD code is useful for applications whose high error detection coverage is very important such as memory systems. Of course, this code can be used in combination with other protection codes which have high correction coverage and low detection coverage. The proposed method is evaluated using more than one billion multiple fault injection experiments. Multiple bit flips were randomly injected in different segments of a memory system and the fault detection and correction coverages are calculated. Results show that 100% of the injected faults can be detected. We proved that, this method can correct up to three bit upsets. Some hardware implementation issues are investigated to show tradeoffs between different implementation parameters of HVD method.

This is a preview of subscription content, access via your institution.

References

  1. 1.

    Hazucha P, Svensson C (2000) Impact of CMOS technology scaling on the atmospheric neutron soft error rate. IEEE Trans Nucl Sci 47(6):2586–2594

    Article  Google Scholar 

  2. 2.

    International Technology Road map for Semiconductors (2002) http://public.itrs.net/

  3. 3.

    Ferreyra PA, Marques CA, Ferreyra RT, Gaspar JP (2005) Failure map functions and accelerated mean time to failure tests: new approaches for improving the reliability estimation in systems exposed to single event upsets. IEEE Trans Nucl Sci 52(1):494–500

    Article  Google Scholar 

  4. 4.

    Karlsson J, Liden P, Dahlgern P, Johansson R, Gunneflo U (1994) Using heavy-ion radiation to validate fault-handling mechanisms. IEEE MICRO 14:8–23

    Article  Google Scholar 

  5. 5.

    Imran M (2006) Using COTS components in space applications. Master Thesis, University of TUDelft

  6. 6.

    Hentschke R, Marques R, Lima F, Carro L, Susin A, Reis R (2002) Analyzing area and performance penalty of protecting different digital modules with hamming code and triple modular redundancy. In: International symposium on integrated circuits and systems design, pp 95–100

    Google Scholar 

  7. 7.

    Reed R (1997) Heavy ion and proton induced single event multiple upsets. In: IEEE nuclear and space radiation effects conference, pp 2224–2229

    Google Scholar 

  8. 8.

    Seifert N, Moyer D, Leland N, Hokinson R (2001) Historical trend in alpha-particle induced soft error rates of the alpha microprocessor. In: Proceeding of 39th annual IEEE international reliability phys symp, pp 259–265

    Google Scholar 

  9. 9.

    Argyrides C, Zarandi HR, Pradhan DK (2007) Multiple upsets tolerance in SRAM memory. In: International symposium on circuits and system, New Orleans, LA, May 2007

    Google Scholar 

  10. 10.

    Rubinoff M N-dimensional codes for detecting and correcting multiple errors. Comun ACM 545–551

  11. 11.

    http://www.eccpage.com/golay23.c

  12. 12.

    Berlekamp ER (1968) Algebraic coding theory. McGraw-Hill, New York

    MATH  Google Scholar 

  13. 13.

    Fill TS, Glenn Gulak P (2002) An assessment of VLSI and embedded software implementations for reed-Solomon decoders. In: Signal processing systems

    Google Scholar 

  14. 14.

    http://mathworld.wolfram.com/GolayCode.html

  15. 15.

    Lin S, Costello DJ Jr (1983) Error control coding: fundamentals and applications. Prentice-Hall, Englewood Cliffs. ISBN 0-13-283796-X

    Google Scholar 

  16. 16.

    Thirunavukkarasu U, Babu Anne N, Latifi S (2004) Three and four-dimensional parity-check codes for correction and detection of multiple errors. In: International conference on information technology: coding and computing, p 480

    Google Scholar 

  17. 17.

    Shirvani PP, Saxena NR, McCluskey EJ (2000) Software-implemented EDAC protection against SEUs. IEEE Trans Reliab 3:273–284

    Article  Google Scholar 

  18. 18.

    Underwood CI, Oldfield MK (2000) Observations on the reliability of COTS-device-based solid state data recorders operating in low-earth orbit. IEEE Trans Nucl Sci 47:647–653

    Article  Google Scholar 

  19. 19.

    Togneri R, deSilva CJS (2002) Fundamentals of information theory and coding design, discrete mathematics and its applications. CRC Press, New York. ISBN 1-58488-310-3

    Google Scholar 

  20. 20.

    Pflanz M, Walther K, Galke C, Vierhaus HT (2004) On-line techniques for error detection and correction in processor registers with cross-parity check. J Electron Test Appl doi:10.1023/A:1025165712071

    Google Scholar 

  21. 21.

    Hyun Yoon D, Erez M (2009) Memory mapped ECC: low-cost error protection for last level caches. ACM SIGARCH Comput Archit News 37(3):116–127

    Article  Google Scholar 

  22. 22.

    http://www.synopsys.com/home.aspx

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Behnam Ghavami.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Kishani, M., Zarandi, H.R., Pedram, H. et al. HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors. Des Autom Embed Syst 15, 289–310 (2011). https://doi.org/10.1007/s10617-011-9078-2

Download citation

Keywords

  • Error detection
  • Error correction
  • Soft errors
  • Multiple bit upsets
  • Vulnerability