During the functional verification, complex interactions between multiple blocks that compose an Intellectual Property (IP) core can reveal hard-to-find bugs. Functional verification specifications must be precise to assure these interactions occur during the simulation. In this work, we are proposing a technique for improving the functional verification specification of individual blocks, preserving the occurrence of these interaction scenarios in the composition phase. Our approach was implemented for the VeriSC methodology, a SystemC-based functional verification methodology. After each block that composes the IP core was stand-alone verified, we exploit the composition phase using set theory to increase the coverage numbers and to justify why some of these numbers cannot, or need not, reach 100%. By applying our approach in a MPEG 4 video decoder design, we show how our work can save functional verification time during the hierarchical composition. Using mutation based-tests, we demonstrate that our work can contribute to error detection. Furthermore, we demonstrate the effectiveness of our approach with regard to traditional structural coverage metrics, such as line coverage and branch coverage.
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This work was partially funded by the Brazil IP project.
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Rodrigues, C.L., da Silva, K.R.G., Cunha, H.N. et al. Enhancing IP cores specifications using hierarchical composition and set theory. Des Autom Embed Syst 15, 225–245 (2011). https://doi.org/10.1007/s10617-011-9076-4
- Functional verification
- Intellectual property core
- Set theory
- MPEG 4