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Design Automation for Embedded Systems

, Volume 14, Issue 3, pp 309–326 | Cite as

Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions

  • Garo BournoutianEmail author
  • Alex Orailoglu
Open Access
Article
  • 519 Downloads

Abstract

Today, embedded processors are expected to be able to run algorithmically complex, memory-intensive applications that were originally designed and coded for general-purpose processors. As such, the impact of memory latencies on the execution time increasingly becomes evident. All the while, it is also expected that embedded processors be power-conscientious as well as of minimal area impact, as they are often used in mobile devices such as wireless smartphones and portable MP3 players. As a result, traditional methods for addressing performance and memory latencies, such as multiple issue, out-of-order execution and large, associative caches, are not aptly suited for the mobile embedded domain due to the significant area and power overhead. This paper explores a novel approach to mitigating execution delays caused by memory latencies that would otherwise not be possible in a regular in-order, single-issue embedded processor without large, power-hungry constructs like a Reorder Buffer (ROB). The concept relies on efficiently leveraging both compile-time and run-time information to safely allow non-data-dependent instructions to continue executing in the event of a memory stall. The simulation results show significant improvement in overall execution throughput of approximately 11%, while having a minimal impact on area overhead and power.

Keywords

Embedded processors Data cache Pipeline stalls Compiler assisted hardware 

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Copyright information

© The Author(s) 2010

Authors and Affiliations

  1. 1.CSE DepartmentUniversity of California, San DiegoLa JollaUSA

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