Skip to main content
SpringerLink
Log in

Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors

  • Published:
Design Automation for Embedded Systems Aims and scope Submit manuscript

Abstract

While hardware/software partitioning has been shown to provide significant performance gains, most hardware/software partitioning approaches are limited to partitioning computational kernels utilizing integers or fixed point implementations. Software developers often initially develop an application using floating point representations built-in to most programming languages and later convert the application to a fixed point representation—a potentially time consuming process. In this paper, we present the Arizona Float ⇔ Fixed Hardware Library (AFFHL) consisting of efficient, configurable floating point to fixed point and fixed point to floating point hardware converters. By utilizing these converters, a system’s hardware/software implementation can be separated into a floating point domain consisting of the microprocessor and memory subsystem and a fixed point domain consisting of one or more partitioned hardware coprocessors. This separation enables a rapid hardware/software partitioning approach in which floating point software kernels can be implemented using fixed point hardware coprocessors without the need for application developers to first rewrite software applications as fixed point implementations. We further present an overview of a basic hardware/software partitioning methodology for rapidly partitioning computational kernels within floating point software application to either statically determined fixed point hardware coprocessors or dynamically adaptable fixed point hardware coprocessors in which the required fixed point representation can be dynamically determined and adjusted at runtime.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Arizona Float ⇔ Fixed Hardware Library (AFFHL) (2009). http://www.ece.arizona.edu/~embedded/Research/Float2Fixed#AFFHL

  2. Balboni A, Fornaciari W, Sciuto D (1996) Partitioning and Exploration in the TOSCA Co-Design Flow. In: Proceedings of the international workshop on hardware/software codesign (CODES), pp 62–69

  3. Banerjee P, Bagchi D, Haldar M, Nayak A, Kim V, Uribe R (2004) Automatic conversion of floating-point matlab programs into fixed-point FPGA based hardware design. In: Proceedings of the design automation conference (DAC), pp 484–487

  4. Belanovíc P, Rupp M. (2005) Automated floating-point to fixed-point conversion with the fixify environment. In: International workshop on rapid system prototyping (RSP)

  5. Berkeley Design Technology Inc (2004) http://www.bdti.com/articles/info_eet0207fpga.htm#DSPEnhanced%20FPGAs

  6. Böhm W, Hammes J, Draper B, Chawathe M, Ross C, Rinker R, Najjar W (2002) Mapping a single assignment programming language to reconfigurable systems. J Supercomput 21:117–130

    Article  MATH  Google Scholar 

  7. Chen W, Kosmas P, Leeser M, Rappaport C (2004) An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. In: Proceedings of the international symposium on field-programmable gate arrays (FPGA), pp 97–105

  8. Clark M, Mulligan M, Jackson D, Linebarger D (2005) Accelerating fixed-point design for MB-OFDM UWB systems. Comms Design, January 26

  9. Cmar R, Rijnders L, Schaumont P, Vernalde S, Bolsens I (1999) A methodology and design environment for DSP ASIC fixed point refinement. In: Proceedings of the design automation and test in Europe conference (DATE)

  10. Gajski D, Vahid F, Narayan S, Gong J (1998) SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans VLSI Syst 6(1):84–100

    Article  Google Scholar 

  11. Guo Z, Buyukkurt B, Najjar W, Vissers K (2005) Optimized generation of data-path from C codes. In: Proceedings of the design automation and test in Europe conference (DATE), pp 112–117

  12. Guthaus M, Ringenberg J, Ernst D, Austin T, Mudge T, Brown R (2001) MiBench: A free, commercially representative embedded benchmark suite. IEEE international workshop on workload characterization (WWC)

  13. Henkel J (1999) A low power hardware/software partitioning approach for core-based embedded systems. In: Proceedings of the design automation conference (DAC), pp 122–127

  14. Henkel J, Li Y (1998) Energy-conscious HW/SW-partitioning of embedded systems: A case study on an MPEG-2 encoder. In: Proceedings of the international workshop on hardware/software codesign (CODES), pp 23–27

  15. IEEE. IEEE 754: Standard for Binary Floating-Point Arithmetic. http://grouper.ieee.org/groups/754/

  16. Keane J, Bradley C, Ebeling C (2004) A compiled accelerator for biological cell signaling simulations. In: Proceedings of the international symposium on field-programmable gate arrays (FPGA), pp 233–241

  17. Keding H, Willems M, Coors M, Meyr H (1998) Fridge: A fixed-point design and simulation environment. In: Proceedings of the design automation and test in Europe conference (DATE)

  18. Lee C, Potkonjak M, Mangione-Smith W (1997) MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. In: Proceedings of the international symposium on microarchitecture (MICRO), pp 330–335

  19. Lysecky R, Stitt G, Vahid F (2006) Warp processors. ACM Trans Des Autom Electron Syst 11(3):659–681

    Article  Google Scholar 

  20. Menard D, Chillet D, Charot F, Sentieys O (2002) Automatic floating-point to fixed-point conversion for dsp code generation. In: Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (CASES), pp 270–276

  21. Saldanha L, Lysecky R (2008) Hardware/software partitioning of floating point software applications to fixed-point coprocessor circuits. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES + ISSS)

  22. Shi C, Brodersen RW (2003) An automated floating-point to fixed-point conversion methodology. In: Proceedings of the IEEE international conference on acoustics, speech, and signal processing, pp 529–532

  23. Shi C, Brodersen RW (2004) Automated Fixed-point data-type optimization tool for signal processing and communication systems. In: Proceedings of the design automation conference (DAC)

  24. Stitt G, Vahid F, McGregor G, Einloth B (2005) Hardware/software partitioning of software binaries: A case study of H.264 decode. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES + ISSS), pp 285–290

  25. Stitt G, Vahid F, Nematbakhsh S (2004) Energy savings and speedups from partitioning critical loops to hardware in embedded systems. ACM Trans Embed Comput Syst 3(1):218–232

    Article  Google Scholar 

  26. Venkataramani G, Najjar W, Kurdahi F, Bagherzadeh N, Bohm W (2001) A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. In: Proceedings of the international conference on compiler, architecture and synthesis for embedded systems (CASES)

  27. Villarreal J, Lysecky R, Cotterell S, Vahid F (2001) Loop analysis of embedded applications. University of California Riverside Technical Report UCR-CSE-01-03

  28. Wan M, Ichikawa Y, Lidsky D, Rabaey L (1998) An energy conscious methodology for early design space exploration of heterogeneous DSPs. In: Proceedings of the ISSS custom integrated circuits conference (CICC)

  29. Willems M, Bürsgens V, Keding H, Grötker T, Meyr H (1997) System level fixed-point design based on an interpolative approach. In: Proceedings of the design automation conference (DAC), pp 293–298

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Arizona, Tucson, USA

    Lance Saldanha & Roman Lysecky

Authors
  1. Lance Saldanha
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Roman Lysecky
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Roman Lysecky.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Saldanha, L., Lysecky, R. Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors. Des Autom Embed Syst 13, 139–157 (2009). https://doi.org/10.1007/s10617-009-9044-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10617-009-9044-4

Keywords

Search

Navigation