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Design Automation for Embedded Systems

, Volume 11, Issue 1, pp 49–90 | Cite as

Formal verification of component-based designs

  • Daniel KarlssonEmail author
  • Petru Eles
  • Zebo Peng
Article

Abstract

Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex, and designers handle this increasing complexity by reusing existing components (Intellectual Property blocks). At the same time, the systems must fulfill strict requirements on reliability and correctness.

This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already formally verified by their designers. The components are considered correct given that the environment satisfies certain properties imposed by the component. The methodology verifies the correctness of the glue logic inserted between the components and the interaction of the components through the glue logic. Each such glue logic is verified one at a time using model checking techniques.

Experimental results have shown the efficiency of the proposed methodology and demonstrated that it is feasible to apply such a verification methodology on real-life examples.

Keywords

Formal verification Petri-nets Components IP Model checking Embedded systems Real-time systems 

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Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  1. 1.ESLAB, Department of Computer and Information ScienceLinköpings UniversitetLinköpingSweden

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