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Design Automation for Embedded Systems

, Volume 10, Issue 2–3, pp 105–125 | Cite as

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

  • Nagu Dhanwada
  • Reinaldo A. Bergamaschi
  • William W. Dungan
  • Indira Nair
  • Paul Gramann
  • William E. Dougherty
  • Ing-Chao Lin
Open Access
Article

Abstract

Transaction-Level models have emerged as an efficient way of modeling systems-on-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transaction-based power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.

Keywords

SystemC Transaction level modeling Architecture modeling Power analysis PowerPC CoreConnect 

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Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  • Nagu Dhanwada
    • 1
  • Reinaldo A. Bergamaschi
    • 2
  • William W. Dungan
    • 1
  • Indira Nair
    • 2
  • Paul Gramann
    • 3
  • William E. Dougherty
    • 1
  • Ing-Chao Lin
    • 4
  1. 1.IBM EDA LaboratoryHopewell JunctionUSA
  2. 2.IBM T. J. Watson Research CenterYorktown HeightsUSA
  3. 3.IBM STGRaleighUSA
  4. 4.Department of Computer SciencePennsylvania State UniversityUSA

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