Abstract
Transaction-Level models have emerged as an efficient way of modeling systems-on-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transaction-based power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.
References
Burton, M. and A. Donlin. Transaction-Level Modeling: Above RTL Design and Methodology. http://www.systemc.org.
AMBA - AHB Cycle Level Interface Specification. ARM white paper, available from http://www.arm.com.
Keutzer, K., S. Malik, A.R. Newton, J.M. Rabaey, and A. Sangiovanni-Vincentelli. System-Level Design: Orthogonalization of Concerns and Platform-Based Design. In IEEE Transaction on Computer-Aided Design, 19(12), December 2000.
Gajski, D., J. Zhu, R. Dömer, A. Gerstlauer, and S. Zhao. SpecC: Specification Language and Design Methodology. Kluwer Academic Publishers, 2000.
The Open SystemC Initiative. http://www.systemc.org.
Grotker, T., S. Liao, G. Martin, and S. Swan . System Design with SystemC. Kluwer Academic Publishers, 2002.
CoreConnectTM Bus Architecture documents, available from http://www.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect_Bus_Architecture.html.
SoC design with CoreConnect: 128-bit PLB explained. tutorial available from http://www.ibm.com/developerworks/edu/pa-dw-pa-socdesign-i.html.
Instruction-Set Simulator User’s Guide. available from IBM under license at http://www.ibm.com/chips/power/licensing/.
RISCWatch Debugger. links and documentation available from: http://www-03.ibm.com/chips/power/tools/riscwatc.html.
Benini, L., D. Bertozzi, D. Bruni, N. Drago, F. Fummi, M. Poncino. Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. In Proceedings 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), IEEE, 494, 2002.
Givargis, T.D., F. Vahid, and J. Henkel. Instruction-Based System-Level Power Evaluation of System-on-a-chip Peripherals. In Proceedings of the 13th International Symposium on System Synthesis (ISSS), 2000.
Caldari, M., M. Conti, M. Coppola, P. Crippa, S. Orcioni, L. Pieralisi, and C. Turchetti. System-Level Power Analysis Methodology Applied to the AMBA AHB Bus. DATE 2003.
Qu, G., N. Kawabe, K, Usame, and M. Potkonjak. Function-Level Power Estimation Methodology for Microprocessors. In Proceedings of the 37th DAC, 2000.
Zhong, L., S. Ravi, A. Raghunathan, and N.K. Jha. Power Estimation for Cycle-Accurate Functional Descriptions of Hardware. In Proceedings of ICCAD, 2004.
Shafi, H., P.J. Bohrer, J. Phelan, C.A. Rusu, and J.L. Peterson. Design and Validation of a Performance and Power Simulator for PowerPC systems. IBM Journal of Research and Development, 47(5/6), September/November 2003.
Devins, R. SoC Verification Software—Test Operating System. IEEE/DATC Electronic Design Processes Workshop, April 2001.
Meet the PowerPC 405 Evaluation Kit. DeveloperWorks web site http://www.ibm.com/developerworks/library/pa-pek/index.html.
Dhanwada, N., I. Lin, and V. Narayanan. A Power Estimation Methodology for SystemC Transaction Level Models. In Proceedings of CODES+ISSS, 2005.
Author information
Authors and Affiliations
Rights and permissions
Open Access This is an open access article distributed under the terms of the Creative Commons Attribution Noncommercial License ( https://creativecommons.org/licenses/by-nc/2.0 ), which permits any noncommercial use, distribution, and reproduction in any medium, provided the original author(s) and source are credited.
About this article
Cite this article
Dhanwada, N., Bergamaschi, R.A., Dungan, W.W. et al. Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. Des Autom Embed Syst 10, 105–125 (2005). https://doi.org/10.1007/s10617-006-9586-7
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10617-006-9586-7
Keywords
- SystemC
- Transaction level modeling
- Architecture modeling
- Power analysis
- PowerPC
- CoreConnect