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Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Abstract

Transaction-Level models have emerged as an efficient way of modeling systems-on-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transaction-based power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.

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Open Access This is an open access article distributed under the terms of the Creative Commons Attribution Noncommercial License ( https://creativecommons.org/licenses/by-nc/2.0 ), which permits any noncommercial use, distribution, and reproduction in any medium, provided the original author(s) and source are credited.

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Dhanwada, N., Bergamaschi, R.A., Dungan, W.W. et al. Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. Des Autom Embed Syst 10, 105–125 (2005). https://doi.org/10.1007/s10617-006-9586-7

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  • DOI: https://doi.org/10.1007/s10617-006-9586-7

Keywords

  • SystemC
  • Transaction level modeling
  • Architecture modeling
  • Power analysis
  • PowerPC
  • CoreConnect