Design Automation for Embedded Systems

, Volume 10, Issue 2–3, pp 105–125 | Cite as

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

  • Nagu Dhanwada
  • Reinaldo A. Bergamaschi
  • William W. Dungan
  • Indira Nair
  • Paul Gramann
  • William E. Dougherty
  • Ing-Chao Lin
Open Access


Transaction-Level models have emerged as an efficient way of modeling systems-on-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transaction-based power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.


SystemC Transaction level modeling Architecture modeling Power analysis PowerPC CoreConnect 


  1. 1.
    Burton, M. and A. Donlin. Transaction-Level Modeling: Above RTL Design and Methodology.
  2. 2.
    AMBA - AHB Cycle Level Interface Specification. ARM white paper, available from
  3. 3.
    Keutzer, K., S. Malik, A.R. Newton, J.M. Rabaey, and A. Sangiovanni-Vincentelli. System-Level Design: Orthogonalization of Concerns and Platform-Based Design. In IEEE Transaction on Computer-Aided Design, 19(12), December 2000.Google Scholar
  4. 4.
    Gajski, D., J. Zhu, R. Dömer, A. Gerstlauer, and S. Zhao. SpecC: Specification Language and Design Methodology. Kluwer Academic Publishers, 2000.Google Scholar
  5. 5.
    The Open SystemC Initiative.
  6. 6.
    Grotker, T., S. Liao, G. Martin, and S. Swan . System Design with SystemC. Kluwer Academic Publishers, 2002.Google Scholar
  7. 7.
  8. 8.
    SoC design with CoreConnect: 128-bit PLB explained. tutorial available from
  9. 9.
    Instruction-Set Simulator User’s Guide. available from IBM under license at
  10. 10.
    RISCWatch Debugger. links and documentation available from:
  11. 11.
    Benini, L., D. Bertozzi, D. Bruni, N. Drago, F. Fummi, M. Poncino. Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. In Proceedings 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), IEEE, 494, 2002.Google Scholar
  12. 12.
    Givargis, T.D., F. Vahid, and J. Henkel. Instruction-Based System-Level Power Evaluation of System-on-a-chip Peripherals. In Proceedings of the 13th International Symposium on System Synthesis (ISSS), 2000.Google Scholar
  13. 13.
    Caldari, M., M. Conti, M. Coppola, P. Crippa, S. Orcioni, L. Pieralisi, and C. Turchetti. System-Level Power Analysis Methodology Applied to the AMBA AHB Bus. DATE 2003.Google Scholar
  14. 14.
    Qu, G., N. Kawabe, K, Usame, and M. Potkonjak. Function-Level Power Estimation Methodology for Microprocessors. In Proceedings of the 37th DAC, 2000.Google Scholar
  15. 15.
    Zhong, L., S. Ravi, A. Raghunathan, and N.K. Jha. Power Estimation for Cycle-Accurate Functional Descriptions of Hardware. In Proceedings of ICCAD, 2004.Google Scholar
  16. 16.
    Shafi, H., P.J. Bohrer, J. Phelan, C.A. Rusu, and J.L. Peterson. Design and Validation of a Performance and Power Simulator for PowerPC systems. IBM Journal of Research and Development, 47(5/6), September/November 2003.Google Scholar
  17. 17.
    Devins, R. SoC Verification Software—Test Operating System. IEEE/DATC Electronic Design Processes Workshop, April 2001.Google Scholar
  18. 18.
    Meet the PowerPC 405 Evaluation Kit. DeveloperWorks web site
  19. 19.
    Dhanwada, N., I. Lin, and V. Narayanan. A Power Estimation Methodology for SystemC Transaction Level Models. In Proceedings of CODES+ISSS, 2005.Google Scholar

Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  • Nagu Dhanwada
    • 1
  • Reinaldo A. Bergamaschi
    • 2
  • William W. Dungan
    • 1
  • Indira Nair
    • 2
  • Paul Gramann
    • 3
  • William E. Dougherty
    • 1
  • Ing-Chao Lin
    • 4
  1. 1.IBM EDA LaboratoryHopewell JunctionUSA
  2. 2.IBM T. J. Watson Research CenterYorktown HeightsUSA
  3. 3.IBM STGRaleighUSA
  4. 4.Department of Computer SciencePennsylvania State UniversityUSA

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