Reducing the complexity of instruction-level power models for VLIW processors

Abstract

Aim of this paper is to propose a high-level power exploration framework based on an instruction-level energy model for VLIW (Very Long Instruction Word) architectures. More specifically, the present paper deals with the reduction of the complexity of the energy model of K-issue VLIW processors from exponential with respect to the number of operations within the Instruction Set O(⫨ISAK) to quadratic (O(K*⫨ISA2)). The complexity of the energy model has been further simplified by automatically clustering the operations in the ISA with respect to their average energy. Globally, the proposed approach reduces the complexity of the characterization problem for a K-issue VLIW processor to quadratic (O(K*⫨C2)) with respect to the number of operation clusters. In this way, a more efficient characterization of the VLIW core power consumption can been achieved, while preserving the accuracy of the power estimates. The proposed model has been further extended to provide early power figures and energy/performance trade-offs for multi-cluster VLIW architectures composed of multiple data-path units and a single instruction cache control unit. The proposed high-level power estimation methodology has been applied to the Lx 4-issue VLIW pipelined processor provided by STMicroelectronics.

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Correspondence to C. Silvano.

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Bona, A., Sami, M., Sciuto, D. et al. Reducing the complexity of instruction-level power models for VLIW processors. Des Autom Embed Syst 10, 49–67 (2005). https://doi.org/10.1007/s10617-006-9045-5

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Keywords

  • Low-power design
  • Power modeling
  • VLIW architectures