During early design phases performance evaluation becomes increasingly important since major system-level decisions, such as the allocation of hardware resources and the partitioning of functionality onto architecture building blocks, affect the quality of the design significantly. Quantitative analysis is hard to achieve due to growing complexities, heterogeneity, and concurrency of modern embedded systems. We propose the use of multiclass queuing networks during the specification phase of the design flow for modeling data-flow oriented systems. Starting from an executable high-level queuing model our evaluation framework SystemQ1 enables successive and systematic refinement of behavior and structure towards established TLM and RTL models based on SystemC. We demonstrate why SystemQ’s multiclass queuing networks are a natural and feasible abstraction for evaluating network processing platforms. In particular we reveal the impact of scheduling policies on the Quality-of-Service, such as the residence time of network traffic in the system. In our case study, we show how stepwise refinement can reduce memory and latency bounds by up to two orders of magnitude and how the choice of only one queuing discipline can affect these properties. The investigated simulation models run in the range of 1 : 100 to 1 : 1 of real-time on a common off-the-shelf Linux PC.
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Sonntag, S., Gries, M. & Sauer, C. SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC. Des Autom Embed Syst 11, 91–117 (2007). https://doi.org/10.1007/s10617-006-9002-3
- Performance evaluation
- Queuing networks
- Access network
- System on chip