Abstract
During early design phases performance evaluation becomes increasingly important since major system-level decisions, such as the allocation of hardware resources and the partitioning of functionality onto architecture building blocks, affect the quality of the design significantly. Quantitative analysis is hard to achieve due to growing complexities, heterogeneity, and concurrency of modern embedded systems. We propose the use of multiclass queuing networks during the specification phase of the design flow for modeling data-flow oriented systems. Starting from an executable high-level queuing model our evaluation framework SystemQ1 enables successive and systematic refinement of behavior and structure towards established TLM and RTL models based on SystemC. We demonstrate why SystemQ’s multiclass queuing networks are a natural and feasible abstraction for evaluating network processing platforms. In particular we reveal the impact of scheduling policies on the Quality-of-Service, such as the residence time of network traffic in the system. In our case study, we show how stepwise refinement can reduce memory and latency bounds by up to two orders of magnitude and how the choice of only one queuing discipline can affect these properties. The investigated simulation models run in the range of 1 : 100 to 1 : 1 of real-time on a common off-the-shelf Linux PC.
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References
Agilent Technologies. JTC 003: Mixed Packet Size Throughput. In The Journal of Internet Test Methodologies, Agilent Technologies, pp. 16–18, 2004.
Balarin, F., Y. Watanabe and H. Hsieh et al. Metropolis: An Integrated Electronic System Design Environment. IEEE Computer, 36(4):45–52, 2003.
Baskett, F., K.M. Chandy, R.R. Muntz and F.G. Palacios. Open, Closed and Mixed Networks of Queues with Different Classes of Customers. Journal of the Association for Computing Machinery, 22(2):248–260, 1975.
Bergamaschi, R.A., Y. Shin, N.R. Dhanwada et al. SEAS: A System for Early Analysis of SoCs. In International Conference on Hardware/Software Co-design and System Synthesis (CODES+lSSS), pp. 150–155, 2003.
de Kock, E.A., G. Essink, W.J.M. Smits et al. YAPI: Application Modeling for Signal Processing Systems. In 37th Design Automation Conference (DAC), 402–405, 2000.
DSL Forum. Multi-Service Architecture & Framework Requirements. Technical Report TR-058, 2003.
Eker, J. and J. Janneck. Cal language report. Technical Memorandum M03/48, Electronics Research Lab, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, 2003.
Eker, J., J.W. Janneck, E.A. Lee et al. Taming Heterogeneity— The Ptolemy approach. Proceedings of the IEEE, 91(1):127–144, 2003.
Grütker, T., S. Liao, G. Martin and S. Swan. System Design with System C. Kluwer Academic Publishers, 2002.
Jackson, J.R. Networks of Waiting Lines. Operations Research, 5:518–521, 1957.
Jain, R. The Art of Computer Systems Performance Analysis: Techniques for Experimental Design, Measurement, Simulation and Modeling. John Wiley & Sons, Inc., 1991.
Keutzer, K., S. Malik, A.R. Newton et al. System-level Design: Orthogonalization of Concerns and Platform-based Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12):1523–1543, 2000.
Kleinrock, L. Queueing Systems, Volume I: Theory. John Wiley & Sons, Inc., 1975.
Kohler, E., R. Morris, B. Chen et al. The Click Modular Router. ACM Transactions on Computer Systems, 18(3):263–297, 2000.
Lazowska, E.D., J. Zahorjan, G.S. Graham and K.C. Sevcik. Quantitative System Performance: Computer System Analysis Using Queueing Network Models. Prentice-Hall, Inc., 1984.
Lilja, D.J. Measuring Computer Performance: A Practitioner's Guide. Cambridge University Press, 2000.
Mentor Graphics, Corp. VStationPRO High-Performance System Verification. Data sheet, 2003.
Murata, T. Petri nets: Properties, Analysis and Applications. Proceedings of the IEEE, 77(4):541–580, 1989.
Open SystemC Initiative. http://www.systemc.org/, Aug. 2006.
Paulin, P.G., C. Pilkington and E. Bensoudane. StepNP: A System-level Exploration Platform for Network Processors. IEEE Design & Test of Computers, 19(6):17–26, 2002.
Pimentel, A.D. The Artemis Workbench for System-level Performance Evaluation of Embedded Systems. International Journal of Embedded Systems, 1(7), 2005.
Pimentel, A.D., L.O. Hertzberger, P. Lieverse et al. Exploring Embedded-Systems Architectures with Artemis. IEEE Computer, 34(11):57–63, 2001.
R Development Core Team. R: A Language and Environment for Statistical Computing. R Foundation for Statistical Computing, Vienna, Austria, 2005.
Rolia, J.A. and K.C. Sevcik. The Method of Layers. IEEE Transactions on Software Engineering, 21(8):689–700, 1995.
Sauer, C., M. Gries and S. Sonntag. Modular Reference Implementation of an IP-DSLAM. In 10th IEEE Symposium on Computers and Communications (ISCC), 191–198, 2005.
Sonntag, S., M. Gries and C. Sauer. SystemQ: A Queuing-based Approach to Architecture Performance Evaluation with SystemC. In Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS, V). vol. 3553 of Lecture Notes in Computer Science, Springer-Verlag, 434–444, 2005.
Sonntag, S., M. Gries and C. Sauer. Performance Evaluation of Packet Processing Architectures Using Multiclass Queuing Networks. In 39th Annual Simulation Symposium, 80–87, 2006.
Wieferink, A., T. Kogel and R. Leupers et al. A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms. In Proceedings of the conference on Design, Automation and Test in Europe (DATE). 2004.
Ykman-Couvreur, C., J. Lambrecht, D. Verkest et al. System-level Performance Optimization of the Data Queueing Memory Management in High-speed Network Processors. In 39th Design Automation Conference (DAC), 518–523, 2002.
Zhu, X., W. Qin and S. Malik. Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation. In International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), 66–71, 2004.
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Sonntag, S., Gries, M. & Sauer, C. SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC. Des Autom Embed Syst 11, 91–117 (2007). https://doi.org/10.1007/s10617-006-9002-3
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DOI: https://doi.org/10.1007/s10617-006-9002-3