In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications.
This is a preview of subscription content, access via your institution.
Buy single article
Instant access to the full article PDF.
Tax calculation will be finalised during checkout.
Subscribe to journal
Immediate online access to all issues from 2019. Subscription will auto renew annually.
Tax calculation will be finalised during checkout.
Hartenstein, R. A Decade of Reconfigurable Computing: A Visionary Retrospective. In Proc. of IEEE/ACM Design Automation and Test in Europe (DATE), pp. 642–649, 2001.
Kastner, R., A. Kaplan, S.O. Memik, and E. Bozorgadeh. Instruction Generation for Hybrid Reconfigurable Systems. In ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 7, no. 4, pp. 605–627, October 2002.
Wan, M., H. Zhang, V. George, M. Benes, A. Abnous, V. Prabhu, and J. Rabaey, Design methodology of a low-energy reconfigurable single-chip DSP system. In Journal of VLSI Signal Processing, vol.28, no. 1–2, pp.47–61, May-June 2001.
Rauwerda, G.K., P.M. Heysters, and G.J.M. Smit. Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture. In the Journal of Supercomputing, Springer-Verlag, vol. 30, no. 3, pp. 263–282, December 2004.
Singh, H., L. Ming-Hau, L. Guangming, F.J. Kurdahi, N. Bagherzadeh, and E.M. Chaves Filho. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Communication-Intensive Applications. In IEEE Trans. on Computers, vol. 49, no. 5, pp. 465–481, May 2000.
Brisk, P., A. Kaplan, R. Kastner, and M. Sarrafzadeh. Instruction Generation and Regularity Extraction for Reconfigurable Processors. In Proc. of Compilers, Architectures and Synthesis for Embedded Systems(CASES), October 8–11, France, pp. 262–269, 2002.
Bazargan, K., S. Ogrenci, and M. Sarrafzadeh. Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. In Proc. of ACM DAC ’01, pp. 635–640, 2001.
Guo, Z., B. Buyukkurt, W. Najjar, and K. Vissers. Optimized Generation of Data-path from C Codes for FPGAs. In Proc. of ACM/IEEE DATE ’05, Munich, Germany, pp. 112–117, 2005.
Goldstein, S.C., H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R.R. Taylor. PipeRench: a reconfigurable architecture and compiler. In IEEE Computer, vol. 33, no. 4, pp. 70–77, April 2000.
Suresh, D.C., W.A. Najjar, F. Vahid, J.R. Villareal, and G. Stitt. Profiling tools for Hardware/Software Partitioning of Embedded Applications. In Proc. of Languages Compilers and Tools for Embedded Systems (LCTES), pp.189–198, 2003.
Stitt, G., F. Vahid, and S. Nematbakhsh. Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems. In ACM Trans. on Embedded Computing Systems (TECS), vol. 3, no. 1, pp. 218–232, Feb. 2004.
IEEE 802.11a Wireless LAN standard, http://grouper.ieee.org/groups/802/11/, 2006.
Bister, M., Y. Taeymans, and J. Cornelis. Automatic Segmentation of Cardiac MR Images. Computers in Cardiology, IEEE Computer Society Press, pp.215–218, 1989.
Strobach, P. QSDPCM — A New Technique in Scene Adaptive Coding. In Proc. of 4th European Signal Processing Conf., (EUSIPCO-88), France, pp. 1141–1144, Sep. 1988.
Honeywell Tech., Adaptive Computing Systems Benchmarks, http://www.htc.honeywell.com/projects/acsbench, 2006.
JPEG image compression, http://wwwjpeg.org, 2006.
Virtex FPGAs, Xilinx Inc., http://wwwxilinx.com, 2006.
Stratix FPGAs, Altera Inc., http://wwwaltera.com, 2006.
Gajski, D.D., F. Vahid, S. Narayan, and J. Gong. SpecSyn: An environment supporting the specify-explore-refine paradigm for hardware/software system design. In IEEE Trans. on VLSI Syst., vol. 6, no. 1, pp. 84–100, 1998.
Henkel, J. A low power hardware/software partitioning approach for core-based embedded systems. In Proc. of the 36th ACM/IEEE Design Automation Conference DAC), pp. 122–127, 1999.
Callahan, T.J., J.R. Hauser, and J. Wawrzynek. The Garp Architecture and C Compiler. In IEEE Computer, vol. 33, no. 4, pp. 62–69, April 2000.
Ye, A., N. Shenoy, and P. Baneijee. A C Compiler for a Processor with a Reconfigurable Functional Unit. In Proc. of FPGA, pp. 95–100, 2000.
Stitt G. and F. Vahid. Energy Advantages of Microprocessors Platforms with On-Chip Configurable Logic. In IEEE Design & Test of Computers, vol. 19, no. 6, pp. 36–43, Nov.-Dec. 2002.
Morpho Technologies, Morpho Reconfigurable DSP (rDSP) core, http://wwwmorphotech.com, 2006.
Becker, J., R. Hartenstein, M. Herz, and U. Nadeldinger. Parallelization in Co-Compilation for Configurable Accelerators: A Host/Accelerator Partitioning Compilation Method. In Proc. of ASPDAC ’98, Yokohama, Japan, Feb. 10–13, 1998.
Becker, J., A. Thomas, and M. Scheer. Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processor. In Proc. of IFIP VLSI SoC Conf., pp. 288–293, 2003.
Galanis, M.D., G. Theodoridis, S. Tragoudas, and C. E. Goutis. A Reconfigurable Coarse-Grain Data-Path for Accelerating Computational Intensive Kernels. In Journal of Circuits, Systems and Computers (JCSC), World Scientific Publishers, vol. 14, no. 9, pp. 877–893, August 2005.
De Micheli, G. Synthesis, and Optimization of Digital Circuits, McGraw-Hill, International Editions, 1994.
Levine, J.R., T. Mason, and D. Brown, Lex & Yacc, O’ Reilly Publishers, 1995.
Motomura, M., Y. Aimoto, A. Shibayama, Y. Yabe, and M. Yamashina. An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. In Proc. of IEEE FCCM ’98, pp. 264–266, 1998.
Long P. and H. Amano. WASMII: a Data Driven Computer on a Virtual Hardware. In Proc. of the 1st IEEE FCCM Workshop, California, USA, April 5–7, pp. 33–42, 1993.
Hudson, R.D., D.I. Lehn, and P.M. Athanas. A Run-Time Reconfigurable Engine for Image Interpolation. In Proc. of 6th IEEE FCCM ’98, California, USA, April 15–17, pp. 88–95, 1998.
Kaul, M., R. Vemuri, S. Govindarajan, and I. Ouassis. An Automated Temporal Partitioning Tool for a class of DSP applications. In Proc of Parallel Architectures and Compilation Techniques Conf., (PACT ’98), pp. 22–27, 1998.
SUIF2 compiler, http://suif.stanford.edu/suif/suif2/index.html, 2006.
Smith, M.D. and G. Holloway. An introduction to Machine SUIF and its portable libraries for analysis and optimization. Technical Report, Harvard University, July 2002.
Crenshaw, J.W. MATH Toolkit for Real-Time Programming, CMP Books, 2000.
Architectures and Methodologies for Dynamic REconfigurable Logic (AMDREL) project, IST-2001-34379, http://vlsi.ee.duth.gr/amdrel/, 2006.
Synplify Pro, Synplicity Inc., http://wwwsynplicity.com, 2006.
MIPS Inc., http://wwwmips.com, 2006.
About this article
Cite this article
Galanis, M.D., Milidonis, A., Theodoridis, G. et al. A method for partitioning applications in hybrid reconfigurable architectures. Des Autom Embed Syst 10, 27–47 (2005). https://doi.org/10.1007/s10617-006-8732-6
- Hybrid reconfigurable systems
- Coarse-grain reconfigurable hardware