A method for partitioning applications in hybrid reconfigurable architectures


In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications.

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Correspondence to Michalis D. Galanis.

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Galanis, M.D., Milidonis, A., Theodoridis, G. et al. A method for partitioning applications in hybrid reconfigurable architectures. Des Autom Embed Syst 10, 27–47 (2005). https://doi.org/10.1007/s10617-006-8732-6

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  • Hybrid reconfigurable systems
  • Partitioning
  • Coarse-grain reconfigurable hardware
  • FPGA
  • scheduling