Estimating data bus size for custom processors in embedded systems


We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulation-based tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.

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  1. 1.

    Chatterjee, A., P. Ellervee, V.J. Mooney, J.C. Park, K-W. Choi, and K. Puttaswamy. System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory. In Proceedings of the 15th international symposium on System Synthesis, 2002.

  2. 2.

    Citron, D. Exploiting Low Entropy to Reduce Wire Delay. In Computer Architecture Letters, volume 3, Jan. 2004.

  3. 3.

    Evans, M.J. and J.S. Rosenthal. Probability and Statistics, The Science of Uncertainty. W.H. Freeman and Company, New York, 2004.

    Google Scholar 

  4. 4.

    Gasteier, M. and M. Glesner. Bus-based communication synthesis on system level. ACM Transactions on Design Automation of Electronics Systems, 4(1), Jan. 1999.

  5. 5.

    Ramazan Gençay, Faruk Selçuk, and Abdurrahman Ulugülyağcı. EVIM: A Software Package for Extreme Value Analysis in MATLAB. Studies in Nonlinear Dynamics and Econometrics, 5(3), Oct. 2001.

  6. 6.

    Givargis, T. and F. Vahid. Interface Exploration for Reduced Power in Core-Based Systems. In International Symposium on System Synthesis (ISSS), Dec. 1998.

  7. 7.

    Guthaus, M.R., J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown. MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In the IEEE 4th Annual Workshop on Workload Characterization, Austin, TX, Dec. 2001.

  8. 8.

    Ho, R., W. Mai, and M.A. Horowitz. The Future of Wires. Proceedings of the IEEE, 89(4), April 2001.

  9. 9.

    Komatsu, S., M. Ikeda, and K. Asada. Bus Data Encoding with Coupling-driven Adaptive Code-book Method for Low Power Data Transmission. In 27th European Solid State Circuits Conference, Villach, Austria, Sep. 2001.

  10. 10.

    Kotz, S. and S. Nadaraj. Extreme Value Distributions, Theory and Applications. Imperial College Press, 2000.

  11. 11.

    Kretzschmar, C., R. Siegmund, and D. Müller. Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses. In Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation: 10th International Workshop (PATMOS 2000), Sep. 2000.

  12. 12.

    Law, A.M. and W.D. Kelton. Simulation Modeling and Analysis. McGraw Hill, 3rd ed., 2000.

  13. 13.

    Lee, C., M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In Proceedings of the 30th Annual IEEE/ACM International Conference on Microarchitecture (Micro-30), Raleigh, N.C., Dec. 1997.

  14. 14.

    Lemieux, J. Introduction to ARM Thumb,, 2003.

  15. 15.

    Lv, T., J. Henkel, H. Lekatsas, and W. Wolf. An Adaptive Dictionary Encoding Scheme for SOC Data Buses. In Proceedings of the conference on Design, Automation and Test in Europe (DATE), 2002.

  16. 16.

    Narayan, S. and D.D. Gajski. Synthesis of System-Level Bus Interfaces. In Proceedings of the European Conference on Design Automation (EDAC), 1994.

  17. 17.

    Pandey, S., H. Zimmer, M. Glesner, and M. Mühlhäuser. High level hardware software communication estimation in shared memory architecture. In IEEE International Symposium on Circuit and Systems (ISCAS′2005), Kobe, Japan, May 2005.

  18. 18.

    Rabaey, J.M., A. Chandrakasan, and B. Nikolić. Digital Integrated Circuits. Prentice Hall Electronics and VLSI Series, 2003.

  19. 19.

    Ramprasad, S., N.R. Shanbhag, and I.N. Hajj. A Coding Framework for Low-power Address and Data busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(2), June 1999.

  20. 20.

    Reiss, R.D. and M. Thomas. Statistical Analysis of Extreme Values. Birkhäuser Verlag, Basel, Switzerland, 1997.

    Google Scholar 

  21. 21.

    Shin, Y. and T. Sakurai. Coupling-Driven Bus Design for Low-Power Application-Specific Systems. In the 38th Annual ACM/IEEE Conference on Design Automation, Las Vegas, 2001.

  22. 22.

    Sotiriadis, P.P. and A. Chandrakasan. Low Power Bus Coding Techniques Considering Inter-wire Capacitances. In CICC 2000, May 2000.

  23. 23.

    Sotiriadis, P. and A. Chandrakasan. Reducing Bus Delay in Submicron Technology Using Coding. In IEEE Asia and South Pacific Design Automation Conf., 2001.

  24. 24.

    Stan, M.R. and W.P. Burleson. Bus-Invert Coding for Low Power I/O. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(1), March 1995.

  25. 25.

    Suresh, D.C., B. Agrawal, J. Yang, W. Najjar, and L. Bhuyan. Power Efficient Encoding Techniques for Off-chip Data Buses. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 2003.

  26. 26.

    Bret Victor and Kurt Keutzer. Bus Encoding to Prevent Crosstalk Delay. In International Conference on Computer-Aided Design (ICCAD ′01), Nov. 2001.

  27. 27.

    Williams, J. HCS12 External Bus Design. In Application Note. Freescale Semiconductor, Aug. 2004.

  28. 28.

    Wilson, R.P., R.S. French, C.S. Wilson, S. Amarasinghe, J.M. Anderson, S.W.K. Tjiang, S.W. Liao, C.W. Tseng, M.W. Hall, M.S. Lam, and J.L. Hennessy. SUIF: An Infrastructure for Research on Parallelizing and Optimizing Compilers. Technical report, Computer Systems Laboratory, Stanford University, 1994.

  29. 29.

    Yang, J. and R. Gupta. FV Encoding for Low-Power Data I/O. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, Aug. 2001.

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Corresponding author

Correspondence to Emre Özer.

Additional information

This study was supported by an Enterprise Ireland Research Innovation Fund Grant IF/2002/035.

Emre Özer is now with ARM Ltd., Cambridge, United Kingdom.

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Özer, E., Nisbet, A.P., Gregg, D. et al. Estimating data bus size for custom processors in embedded systems. Des Autom Embed Syst 10, 5–26 (2005).

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  • Buses
  • Custom processors
  • Embedded systems
  • Extreme value theory
  • Statistics