Abstract
We describe a method of polynomial simulation to calculate switching activities in a general-delay logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which has been extended to handle temporal correlation and arbitrary transport delays. The method can target both combinational and sequential circuits.
Our method is parameterized by a single parameter l, which determines the speed-accuracy tradeoff. l indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergent paths whose length is at most l. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error. When l = L, where L is the total number of levels of logic in the circuit, the method will produce the exact switching activity under a zero delay model, taking into account all internal correlation.
We present results that show that the error in the switching activity and power estimates is very small even for small values of l. In fact, for most of the examples, power estimates with l = 0 are within 5% of the exact. However, this error can be higher than 20% for some examples. More robust estimates are obtained with l = 2, providing a good compromise between speed and accuracy.
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References
Bryant, R. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, vol. 35, no. 8, pp. 677–691, 1986.
Cheng, D. Power Estimation of Digital CMOS Circuits and the Application to Logic Synthesis for Low Power. PhD thesis, University of California at Santa Barbara, Dec. 1995.
Chou, T.-L. and K. Roy. Statistical Estimation of Sequential Circuit Activity. In Proceedings of the IEEE International Conference on Computer-Aided Design, Nov. 1995, pp. 34–37.
Cirit, M. Estimating Dynamic Power Consumption of CMOS Circuits. In Proceedings of the IEEE International Conference on Computer-Aided Design, Nov. 1987, pp. 534–537.
Costa, J., J. Monteiro, and S. Devadas. Switching Activity Estimation Using Limited Depth Reconvergent Path Analysis. In Proceedings of the International Symposium on Low Power Electronics and Design, Aug. 1997, pp. 184–189.
Favalli, M., and L. Benini. Analysis of Glitch Power Dissipation in CMOS ICs. In Proceedings of the International Symposium on Low Power Electronics and Design, April 1995, pp. 123-128.
Glasser, L. and D. Dobberpuhl. The Design and Analysis of VLSI Circuits. Addison-Wesley, 1985.
Kapoor, B. Improving the Accuracy of Circuit Activity Measurement. In International Workshop on Low Power Design, April 1994, pp. 111–116.
Lengauer, T. and R. Tarjan. A Fast Algorithm for Finding Dominators in a Flowgraph. ACM Transactions on Programming Languages and Systems, vol. 1, no. 1, pp. 121–141, 1979.
Marculescu, R., D. Marculescu, and M. Pedram. Switching Activity Analysis Considering Spatiotemporal Correlations. In Proceedings of the IEEE International Conference on Computer-Aided Design, Nov. 1994, pp. 294–299.
Monteiro, J. and S. Devadas. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits. Kluwer Academic Publishers, 1996.
Monteiro, J., S. Devadas, A. Ghosh, K. Keutzer, and J. White. Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation. IEEE Transactions on Computer-Aided Design, vol. 16, no. 1, pp. 121–127, 1997.
Najm, F. Transition Density, A Stochastic Measure of Activity in Digital Circuits. In Proceedings of the 28th Design Automation Conference, June 1991, pp. 644–649.
Najm, F. A Survey of Power Estimation Techniques in VLSI Circuits (Invited Paper). IEEE Transactions on VLSI Systems, vol. 2, no. 4, pp. 446–455, 1994.
Najm, F., R. Burch, P. Yang, and I. Hajj. Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits. IEEE Transactions onComputer-Aided Design, vol. 9, no. 4, pp. 439–450, 1990.
Najm, F., S. Goel, and I. Hajj. Power Estimation in Sequential Circuits. In Proceedings of the 32nd Design Automation Conference, June 1995, pp. 635–640.
Nebel, W., and J. Mermet (eds.). Low Power Design in Deep Submicron Electronics. Kluwer Academic Publishers, 1997.
Parker, K. and E. McCluskey. Probabilistic Treatment of General Combinational Networks. IEEE Transactions on Electronic Computers, vol. C-24, no. 6, pp. 668–670, 1975.
Seth, S.C., L. Pan, and V.D. Agrawal. PREDICT: Probabilistic Estimation of Digital Circuit Testability. In Proceedings of the Fault Tolerant Computing Symposium, June 1985, pp. 220–225.
Tsui, C.-Y., J. Monteiro, M. Pedram, S. Devadas, A. Despain, and B. Lin.Power Estimation Methods for Sequential Logic Circuits. IEEE Transactions on VLSI Systems, vol. 3, no. 3, pp. 404–416, 1995.
Tsui, C.-Y., M. Pedram, and A. Despain. Efficient Estimation of Dynamic Power Dissipation under a Real Delay Model. In Proceedings of the IEEE International Conference on Computer-Aided Design, Nov. 1993, pp. 224–228.
Uchino, T., F. Minami, T. Mitsuhashi, and N. Goto. Switching Activity Analysis using Boolean Approximation Method. In Proceedings of the IEEE International Conference on Computer-Aided Design, Nov. 1995, pp. 20–25.
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Costa, J., Silveira, L., Devadas, S. et al. Power Estimation Using Probability Polynomials. Des Autom Embed Syst 9, 19–52 (2004). https://doi.org/10.1007/s10617-005-5344-5
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DOI: https://doi.org/10.1007/s10617-005-5344-5