Skip to main content
SpringerLink
Log in

Reliability improved, high performance FIR filter design using new computation sharing multiplier: suitable for signal processing applications

  • Published:
Cluster Computing Aims and scope Submit manuscript

Abstract

The finite impulse response (FIR) filter are class of digital filter are extensively used in signal processing and in communication system applications such as noise reduction, echo cancellation and image enhancement etc. Designing a FIR filter with less computation time, low power and by using minimum hardware playing a major role in overall performance of the application where FIR filter is involved. The research work presented in this paper has been carried out to fulfil the above said aim. In this research work, 16 tap FIR filter has been implemented using newly proposed floating point Computation Sharing High Speed Multiplier (CSHM). Since in FIR filter, floating point multiplication is involved in each and every tap of filter operation, bringing the floating point multiplication architecture with less computation time, low power and with minimum hardware will automatically improve the performance of FIR filter. The newly proposed computation sharing multiplier differs from existing computation sharing multiplier with respect to fixed alphabet entries in a precomputer unit and efficient computation of distributed arithmetic based vector scalar product. Front end and backend design of a 16 tap FIR filter using newly proposed CSHM and existing CSHM has been carried out using Cadence® nclaunch®, RC® and Encounter® tool with tsmc 180 nm technology library. Comparison result of 16 tap FIR filter shows that 18% reduction in chip power, 13% reduction in chip area and 26% reduction in cell count has been achieved with newly proposed floating point CSHM compare to 16 tap FIR filter designed with existing CHSM. This research work also proposes efficient automation algorithms which improve the design for manufacturability (DFM) of a post layout of a 16 tap FIR filter designed which will improve the reliability of integrated circuits. There are many DFM guidelines have to be followed during layout design. In this research work, the automation algorithm has been proposed for one of the DFM guideline called VIA-Redundancy. The aim of this automation algorithm is to replacing single VIA with double VIA wherever possible. In case of “L” transition routing, single contacts can be very sensitive to resistivity spread and defect. The probability to have too resistive transition will be very much minimized by inserting a new contact which reduces electro-migration effect. Through this automation algorithm redundancy percentage of all the VIA’s of FIR filter designed has been increased without compromising chip area, power and computation time much. The specialty of this automated algorithm is that this can be used to any design which has been implemented on the same platform and technology node. The proposed algorithm automated through Tcl 8.6, UNIX platform.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. Chang, T.-S., Jen, C.-W.: Low power FIR filter realization with differential coefficients and inputs. In: Acoustics, Speech and Signal Processing (1998)

  2. Sankarayya, N., Roy, K., Bhattacharya, D.: Algorithms for low power and high speed FIR filter realization using differential coefficients. IEEE Trans. Circuits Syst. II 44(6), 488–497 (1997)

    Article  Google Scholar 

  3. Mahesh, R., Vinod, A.P.: New reconfigurable architectures for implementing FIR filters with low complexity. IEEE Trans. Comput. Des. Integr. Circuits Syst. 29(2), 275–288 (2010)

    Article  Google Scholar 

  4. Park, J., Muhammad, K., Roy, K.: High performance FIR filter design based on sharing multiplication. IEEE Trans. Large Scale Integr. VLSI Syst. 11(2), 244–253 (2003)

    Article  Google Scholar 

  5. Sivanantham, S., Jagannadha Naidu, K., Balamurugan, S., Bhuvana Phaneendra, D.: Low power floating point computation sharing multiplier for signal processing applications. Int. J. Eng. Technol. 5(2), 979–985 (2013)

    Google Scholar 

  6. Kuo, K.C., Chou, C.W.: Low power and high speed multiplier design with row bypassing and parallel architecture. Microelectron. J. 41(10), 639–650 (2010)

    Article  Google Scholar 

  7. Zervakis, G., Tsoumanis, K., Xydis, S., Axelos, N., Pekmostzi, K.: Approximate multiplier architecture through partial product perforation: Power- Area Tradeoffs analysis. In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, pp. 229–232 (2015)

  8. Umadevi, S., Vigneswaran, T., Vinay, S.K., Seerengasamy, V.: A novel, less area computation sharing high speed multiplier architecture for FIR filter design. Res. J. Appl. Sci. Eng. Technol. 10(7), 816–823 (2015)

    Article  Google Scholar 

  9. Xi, J.G.: Improving yield in RTL-to-GDSII Fluws. In: EE Times, Accessed 11 July 2005

  10. Fujimaki, T., Higashi, K., Nakamura, N., Matsunaga, N., Yoshida, K., Miyawaki, N., Hatano, M., Hasunuma, M., Wada, J., Nishioka, T., Akiyama, K., Kawashima, H., Enomoto, Y., Hasegawa, T., Honda, K., Iwai, M., Yamada, S., Matsuoka, F.: Mechanism of moisture uptake induced via failure and its impact on 45 nm node interconnect design. In: Electron Devices Meeting (2005)

  11. Rajkanan, K.: Yield analysis methodology for low defectivity wafer fabs. In: Proc. Int. Workshop Memory Technol., Design, Testing, pp. 65 (2000)

  12. de Dood, P.: Improving yields without compromising area. In: EE Times, Accessed 13 August 2008

  13. Chen, Z.: Layout and logical techniques for yield and reliability enchancement. In: Doctoral Dissertations AAI9841852 (1998)

  14. Chang, T.-F., Kan, T.-C., Yang, S.-H., Ruan, S.-J.: Enhanced redundant via insertion with multi-via mechanisms. In: IEEE Computer Society Annual Symposium on VLSI (2011)

  15. Lee, K.-Y., Lin, S.-T., Wang, T.-C.: Enhanced double via insertion using wire bending. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29(2) (2010)

    Article  Google Scholar 

  16. Lee, K.-Y., Wang, T.-C.: Post routing redundant via insertion for yield/reliability improvement. In: Proc. Asia South Pacific Design Automation Conference, pp. 303–308 (2006)

  17. Luo, F., Jia, Y., Dai, W.W.-M.: Yield-preferred via insertion based on novel geotopological technology. In: Proc. Asia South Pacific Design Automat. Conf., pp. 730–735 (2006)

  18. Fayed, A.A., Bayoumi, M.A.: A novel architecture for low-power design of parallel multipliers. In: Proceedings of the IEEE Computer Society Workshop on VLSI, pp. 149–154 (2001)

  19. Muhammad, K., Roy, K.: Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10(3), pp. 292–300 (2002)

    Article  Google Scholar 

  20. Lee, K.-Y., Wang, T.-C., Chao, K.-Y.: Post routing redundant via insertion and line end extension with via density consideration. In: Proc. Int. Conf. Comput.-Aided Design, pp. 633–640 (2006)

  21. IEDM Technical Digest. IEEE International, 5–5, pp. 183–186 (2005). Taiwan Semiconductor Manufacturing Company (TSMC). Reference Flow 5.0 and Reference Flow 6.0

Download references

Author information

Authors and Affiliations

  1. School of Electronics Engineering, VIT University, Chennai, India

    S. Umadevi & T. Vigneswaran

Authors
  1. S. Umadevi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. T. Vigneswaran
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to T. Vigneswaran.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Umadevi, S., Vigneswaran, T. Reliability improved, high performance FIR filter design using new computation sharing multiplier: suitable for signal processing applications. Cluster Comput 22 (Suppl 6), 13669–13681 (2019). https://doi.org/10.1007/s10586-018-2067-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10586-018-2067-5

Keywords

Search

Navigation