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GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC

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Abstract

Recently, there has been enormous attention given to the network on chip (NoC) because it is scalable compared to the communication bus. Three dimensional (3D) NoC is getting more popular due to the reduction of wire length with that off two dimensional NoC. The router in the NoC is provides communication between the different computational units. In this paper, a two-phase bundled-data handshake latch is used with an asynchronous router. The Mousetrap latch controller forms the basis of this asynchronous router. The major part of the arbiter is to schedule the packet, then deliver to its destination without any loss of the packet. This paper proposes a novel asynchronous 3D lottery routing algorithm which is based on arbitral mechanism. The Lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The proposed hardware is implemented using Cadence 180 nm technology. The result shows that the power reduction is about 17% and a slight increase in area and delay of about 2% with respect to synchronous 3D NoC.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Vel Tech Multi Tech, Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi, Chennai, Tamil Nadu, 600062, India

    A. Karthikeyan

  2. Department of Information Technology, SKR Engineering College, Poonamallee, Chennai, Tamil Nadu, 600069, India

    P. Senthil Kumar

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  1. A. Karthikeyan
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  2. P. Senthil Kumar
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Correspondence to A. Karthikeyan.

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Karthikeyan, A., Kumar, P.S. GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC. Cluster Comput 21, 177–187 (2018). https://doi.org/10.1007/s10586-017-0979-0

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