Abstract
Two models of logic circuits are proposed for the implementation of Mealy FSMs. The models are underlain by FPGAs with embedded memory blocks and are based on a transformation of object codes. To decrease the number of lookup table elements, it is proposed to decrease the number of irregular functions representing FSMs. An example of design and results of experiments are given for the proposed synthesis method based on the transformation of codes of collections of microoperations into state codes of FSMs.
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Translated from Kibernetika i Sistemnyi Analiz, No. 2, pp. 177–187, March–April 2012.
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Barkalov, A.A., Titarenko, L.A. & Barkalov, A.A. Structural decomposition as a tool for the optimization of an FPGA-based implementation of a mealy FSM. Cybern Syst Anal 48, 313–322 (2012). https://doi.org/10.1007/s10559-012-9410-2
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DOI: https://doi.org/10.1007/s10559-012-9410-2