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Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications

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Abstract

This work proposes an optimized Nanosheet Transistor (NSHT) with an inner high-k spacer and an underlap region. A symmetric dual-k spacer structure and an undoped underlap region are incorporated into the baseline device to optimize it for better performance. The optimized NSHT exhibits an improvement of 54% in the on-to-off current ratio (ION/IOFF) and 36% in the off current (IOFF) over the baseline NSHT of 5 nm node. The analog performance of the optimized NSHT is compared with the performance of the baseline NSHT device across the design space. The optimized NSHT, with Lg/Wg = 12 nm/120 nm, shows the largest transconductance (gm) value with a 6.7% increment compared to the baseline device. An increase of 4.9% in the maximum value of Av is obtained in optimized NSHT with Lg/Wg = 12 nm/15 nm, as compared to its baseline counterpart NSHT. Also, the intrinsic gain (Av) of optimized NSHT, with Lg/Wg = 12 nm/120 nm, shows a most significant improvement of 8.6% over its baseline counterpart NSHT. NSHT with Lg/Wg = 12 nm /120 nm has the highest value of unit-gain frequency (fT) for both optimized and baseline structures. Baseline NSHT shows higher fT values. NSHT with Lg/Wg = 12 nm/15 nm shows the highest gain frequency product (GFP). The optimized NSHT device gives a better analog performance in terms of gain (Av). However, the baseline NSHT device will serve the purpose better for analog applications requiring large fT and GFP values.

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Authors and Affiliations

  1. National Institute of Technology Uttarakhand, Srinagar Garhwal, Uttarakhand, 246174, India

    Arvind Bisht, Yogendra Pratap Pundir & Pankaj Kumar Pal

  2. Hemvati Nandan Bahuguna Garhwal University, Srinagar Garhwal, Uttarakhand, 246174, India

    Yogendra Pratap Pundir

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  1. Arvind Bisht
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Contributions

Arvind Bisht has contributed in the Conceptualization, Methodology, Writing Original Draft, Software, Data Curation, Investigation, Formal Analysis, and Editing. Yogendra Pratap Pundir has contributed to the Writing Original Draft and Formal Analysis. Pankaj Kumar Pal has contributed to Formal Analysis and Editing of this paper. All authors have contributed to the revision of the manuscript.

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Correspondence to Yogendra Pratap Pundir.

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Bisht, A., Pundir, Y.P. & Pal, P.K. Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications. Analog Integr Circ Sig Process 116, 35–47 (2023). https://doi.org/10.1007/s10470-023-02171-x

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