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3-D graphics of digital multiplier with Kogge-Stone adder

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Abstract

For 3-D graphic applications requiring powerful, piece-by-piece, second-order polynomial assessments, this paper proposes a novel dual-channel multiplier (NDCM). Generally multiplier plays a key role in any signal processing application. But multipliers will occupy more area and power consumption. Multipliers will consist of adders and shifters. So to increase the speed of multiplier a novel adder is to be designed. The type of adder used to evaluate the multiplier has a significant impact on its performance. Different hardware architectures can be created using the kogge—stone adder and its applications. Traditional dual channel multiplier’s (DCM) drawbacks are eliminated by using the kogge-stone Parallel Prefix adder. Hardware complexity is decreased. The proposed scheme's complicated functions can be meet with a powerful and economical solution. In the piece-wise polynomial approximation, the prefix adder reduces the hardware computer initiative with uniform or uniform segmentation. There is a negligible influence on delay as compared to the large input word size CPA of these devices. The proposed design is synthesized on Xilinx 14.2. The proposed architecture achieves high speed at a reduced area and delay when compared with recent designs. The proposed architecture is implemented and tested on Virtex 5vsx95-1ff1136 FPGA and the results show that the proposed design involves less number of slices and offers high speed than existing designs. The FPGA device utilization summary and latency are analyzed and compared.

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Correspondence to Manne Renuka.

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Renuka, M., Mary Valantina, G. 3-D graphics of digital multiplier with Kogge-Stone adder. Analog Integr Circ Sig Process 113, 343–352 (2022). https://doi.org/10.1007/s10470-022-02087-y

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