Skip to main content
SpringerLink
Log in

An analog circuit analysis method by node elimination

  • Mixed Signal Letter
  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper introduces a node elimination method for analog circuit analysis. It is useful for manually deriving the transfer functions of small active circuit cells in analog integrated circuit design. This method is essentially a variant of Gaussian elimination and can be established based on the driving point impedance method. By successively reducing the circuit size, a circuit can be easily solved as soon as all internal nodes are eliminated. Examples are provided to illustrate the analysis steps.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

Data Availability Statement

Data sharing not applicable to this article as no datasets were generated during the current study.

References

  1. Ochoa, A. (1998). A systematic approach to the analysis of general and feedback circuits and systems using signal flow graphs and driving-point impedance. IEEE Transaction on Circuits and Systems - II Analog and Digital Signal Processing, 45(2), 187–195.

    Article  Google Scholar 

  2. Allen, P. E., & Holberg, D. R. (2002). CMOS Analog Circuit Design (2nd ed.). Oxford University Press.

  3. Pierzchala, M., & Rodanski, B. (2001). Generation of sequential symbolic network functions for large-scale networks by circuit reduction to a two-port. IEEE Transaction on Circuits and Systems-I Fundamental Theory and Applications, 48(7), 906–909.

    Article  Google Scholar 

  4. Rohrer, R. A. (1988). Circuit partitioning simplified. IEEE Transaction on Circuits and Systems, 35(1), 2–5.

    Article  MathSciNet  Google Scholar 

  5. Sánchez-López, C., Fernández, F. V., Tlelo-Cuautle, E., & Tan, S. X. D. (2011). Pathological element-based active device models and their application to symbolic analysis. IEEE Transaction on Circuits and Systems - I: Regular Papers, 58(6), 1382–1395.

    Article  MathSciNet  Google Scholar 

  6. Sheehan, B.N., (1999) TICER: Realizable reduction of extracted RC circuits. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design (pp. 200–203). San Jose, CA, USA

  7. Sheehan, B. N. (2007). Realizable reduction of RC networks. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 26(8), 1393–1407.

    Article  Google Scholar 

  8. Shi, C. J. R., & Tan, X. D. (2000). Canonical symbolic analysis of large analog circuits with determinant decision diagrams. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 19(1), 1–18.

    Article  Google Scholar 

  9. Shi, G. (2013). Graph-pair decision diagram construction for topological symbolic circuit analysis. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 32(2), 275–288.

    Article  Google Scholar 

  10. Shi, G. (2015). Two-graph analysis of pathological equivalent networks. International Journal of Circuit Theory and Applications, 43, 1127–1146.

    Article  Google Scholar 

  11. Shi, G., Hu, B., & Shi, C. J. R. (2006). On symbolic model order reduction. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 25(7), 1257–1272.

    Article  MathSciNet  Google Scholar 

  12. Wang, H. Y., Huang, W. C., & Chiang, N. H. (2010). Symbolic nodal analysis of circuits using pathological elements. IEEE Transaction on Circuits and Systems-II: Express Briefs, 57(11), 874–877.

    Article  Google Scholar 

Download references

Acknowledgements

This research was supported by the National Key R&D Program of China No. 2019YFB2205002 and the National Natural Science Foundation of China (NSFC) grant No. 61974087.

Author information

Authors and Affiliations

  1. Department of Micro/Nano Electronics, School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China

    Guoyong Shi

Authors
  1. Guoyong Shi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Guoyong Shi.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Shi, G. An analog circuit analysis method by node elimination. Analog Integr Circ Sig Process 109, 247–252 (2021). https://doi.org/10.1007/s10470-021-01931-x

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-021-01931-x

Keywords

Search

Navigation