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A 6-bit hierarchal TDC architecture for time-based ADCs

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Abstract

A 6-bit hieratical time-to-digital (TDC) architecture suitable for time-based ADC circuits is presented in this paper. The design consists of similar stages at which each stage recovers one bit. Using the proposed architecture, the total number of bits can be increased without complicating the design as in other conventional TDC architectures. A 6-bit 1.3 Gb/s TDC circuit has been designed and simulated in 28 nm mixed-signal CMOS technology based on the proposed architecture using 5.6 ps time resolution. A Calibration circuit has been designed for each delay line in order to tolerate the variations due to process and mismatch between transistors, which affect the designed delay lines in the design. Monte-Carlo simulations have been done to the designed TDC before and after using the calibration circuit. The calibration circuit corrects the delay line values with an error of ± 2%. The INL and the DNL accuracy of the designed TDC are less than 0.5 LSB and 0.4 LSB. The power consumption of the designed 6-bit TDC circuit is less than 1.3 mW including the calibration circuits.

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Acknowledgements

This work was supported by the Electrical Engineering Dept. at the University of Calgary.

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  1. Faculty of Energy Engineering, Aswan University, Aswân, Egypt

    Mostafa Rashdan

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  1. Mostafa Rashdan
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Correspondence to Mostafa Rashdan.

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Rashdan, M. A 6-bit hierarchal TDC architecture for time-based ADCs. Analog Integr Circ Sig Process 107, 15–27 (2021). https://doi.org/10.1007/s10470-020-01734-6

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