Variation-tolerant, low-power, and high endurance read scheme for memristor memories


Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristor-based memory design. This paper presents a novel read scheme that achieves a non-destructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses built-in self-tuning circuitry to obtain the optimum amplitude and width of the refresh pulse required to completely retrieve the state of the memristor after the read cycle. As the scheme uses refresh pulse only when needed, the scheme saves nearly 50% of average power when compared with a conventional fixed pulse read method. The self-tuning circuits are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” model. The validation results prove that the proposed tuning circuitry achieves optimum refresh pulse size under various read disturbance faults.

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  1. 1.

    Ageev, O. A., Blinov, Y. F., Ilin, O. I., Kolomiitsev, A. S., Konoplev, B. G., Rubashkina, M. V., et al. (2013). Memristor effect on bundles of vertically aligned carbon nanotubes tested by scanning tunnel microscopy. Technical Physics, 58(12), 1831–1836.

    Article  Google Scholar 

  2. 2.

    Bao, B., Hu, A., Bao, H., Xu, Q., Chen, M., & Wu, H. (2018). Three-dimensional memristive Hindmarsh–Rose neuron model with hidden coexisting asymmetric behaviors. Complexity 2018, 3872573.

  3. 3.

    Bao, B., Qian, H., Quan, X., Chen, M., Wang, J., & Yajuan, Yu. (2017). Coexisting behaviors of asymmetric attractors in hyperbolic-type memristor based hopfield neural network. Frontiers in Computational Neuroscience, 11, 81.

    Article  Google Scholar 

  4. 4.

    Berzina, T., Smerieri, A., Ruggeri, G., Erokhin, V., & Fontana, M. P. (2010). Role of the solid electrolyte composition on the performance of a polymeric memristor. Materials Science and Engineering C, 30(3), 407–411.

    Article  Google Scholar 

  5. 5.

    Chanthbouala, A., Garcia, V., Cherifi, R. O., Bouzehouane, K., Fusil, S., Moya, X., et al. (2012). A ferroelectric memristor. Nature Materials, 11(10), 860.

    Article  Google Scholar 

  6. 6.

    Chen, C.-Y., Shih, H.-C., Cheng-Wen, W., Lin, C.-H., Chiu, P.-F., Sheu, S.-S., et al. (2014). RRAM defect modeling and failure analysis based on March test and a novel squeeze-search scheme. IEEE Transactions on Computers, 1, 1.

    Article  Google Scholar 

  7. 7.

    Chen, P.-s., Chen, Y.-s., Tsai, K.-h., & Lee, H.-y. (2013). Microelectronic engineering polarity dependence of forming step on improved performance in Ti/HfOx/W with dual resistive switching mode. Microelectronic Engineering, 112, 157–162.

    Article  Google Scholar 

  8. 8.

    Dongale, T. D., Khot, K. V., Mohite, S. V., Desai, N. D., Shinde, S. S., Patil, V. L., et al. (2017). Effect of write voltage and frequency on the reliability aspects of memristor-based RRAM. International Nano Letters, 7(3), 209–216.

    Article  Google Scholar 

  9. 9.

    Dongale, T. D., Khot, K. V., Mohite, S. V., Desai, N. K., Shinde, S. S., Moholkar, A. V., et al. (2017). Investigating reliability aspects of memristor based RRAM with reference to write voltage and frequency. International Nano Letters, 7(3), 209–216.

  10. 10.

    Dongale, T. D., Patil, K. P., Mullani, S. B., More, K. V., Delekar, S. D., Patil, P. S., et al. (2015). Investigation of process parameter variation in the memristor based resistive random access memory (RRAM): effect of device size variations. Materials Science in Semiconductor Processing, 35, 174–180.

    Article  Google Scholar 

  11. 11.

    Ebong, I. E., & Mazumder, P. (2011). Self-controlled writing and erasing in a memristor crossbar memory. IEEE Transactions on Nanotechnology, 10(6), 1454–1463.

    Article  Google Scholar 

  12. 12.

    Elshamy, M., Mostafa, H., Ghallab, Y. H., & Said, M. S. (2014). A novel nondestructive read/write circuit for memristor-based memory arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(11), 2648–2656.

  13. 13.

    Eshraghian, K., Cho, K. R., Kavehei, O., Kang, S. K., Abbott, D., & Kang, S. M. S. (2011). Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(8), 1407–1417.

    Article  Google Scholar 

  14. 14.

    Fouad, A. H., & Radwan, A. G. (2019). Memristor-based quinary half adder. AEU-International Journal of Electronics and Communications, 98, 123–130.

    Article  Google Scholar 

  15. 15.

    Ghofrani, A., Gaba, S., Payvand, M., Wei, L., Theogarajan, L., & Cheng, K.-T. (2015). A low-power variation-aware adaptive write scheme for access-transistor-free memristive memory. ACM Journal on Emerging Technologies in Computing Systems (JETC), 12(1), 3.

    Google Scholar 

  16. 16.

    Ghofrani, A., Lastras-Montano, M. A., & Cheng, K. T. (2013). Towards data reliable crossbar-based memristive memories. In Proceedings-international test conference.

  17. 17.

    Hamdioui, S., Senior Member, Taouil, M., & Student Member. (2015). Testing open defects in memristor-based memories. 64(1):247–59.

  18. 18.

    Hamdioui, S., Taouil, M., & Haron, N. Z. (2015). Testing open defects in memristor-based memories. IEEE Transactions on Computers, 64(1), 247–259.

    MathSciNet  Article  Google Scholar 

  19. 19.

    Hamdioui, S., Xie, L., Nguyen, H. A. D., Taouil, M., Bertels, K., Corporaal, H., Jiao, H., Catthoor, F., Wouters, D., & Eike, L. (2015). Memristor based computation-in-memory architecture for data-intensive applications. In Proceedings of the 2015 design, automation & test in Europe conference & exhibition (pp. 1718–1725). EDA Consortium.

  20. 20.

    Ho, Y., Huang, G. M., & Li, P. (2011). Dynamical properties and design analysis for nonvolatile memristor memories. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(4), 724–736.

    MathSciNet  Article  Google Scholar 

  21. 21.

    Indiveri, G., Linares-Barranco, B., Legenstein, R., Deligeorgis, G., & Prodromakis, T. (2013). Integration of nanoscale memristor synapses in neuromorphic computing architectures. Nanotechnology, 24(38), 384010.

    Article  Google Scholar 

  22. 22.

    Kannan, S., Karimi, N., Karri, R., & Sinanoglu, O. (2015). Modeling, detection, and diagnosis of faults in multilevel memristor memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(5), 822–834.

    Article  Google Scholar 

  23. 23.

    Karg, S. F., Meijer, G. I., Bednorz, J. G., Rettner, C. T., Schrott, A. G., Joseph, E. A., et al. (2008). Transition-metal-oxide-based resistance-change memories. IBM Journal of Research and Development, 52(45), 481–492.

    Article  Google Scholar 

  24. 24.

    Koveshnikov, S., Matthews, K., Min, K., Gilmer, D. C., Sung, M. G., Deora, S., Li, H. F., Gausepohl, S., Kirsch, P. D., & Jammy, R. (2012). Real-time study of switching kinetics in integrated 1T/HfOx1R RRAM: Intrinsic tunability of set/reset voltage and trade-off with switching time. In Electron devices meeting (IEDM), 2012 IEEE international (pp. 20–24). IEEE.

  25. 25.

    Kvatinsky, S., Ramadan, M., Friedman, E. G., & Kolodny, A. (2015). VTEAM: A general model for voltage-controlled memristors. IEEE Transactions on Circuits and Systems II: Express Briefs, 62(8), 786–790.

    Article  Google Scholar 

  26. 26.

    Kvatinsky, S., Talisveyberg, K., Fliter, D., Kolodny, A., Weiser, U. C., & Friedman, E. G. (2012). Models of memristors for SPICE simulations. In 2012 IEEE 27th convention of electrical and electronics engineers in Israel, IEEEI 2012 (pp. 1–5).

  27. 27.

    Leon, C. (1971). Memristor—The missing circuit element. IEE Transactions on Circuit Theory, 18, 507–519.

    Article  Google Scholar 

  28. 28.

    Li, C., Miao, H., Li, Y., Jiang, H., Ge, N., Montgomery, E., et al. (2018). Analogue signal and image processing with large memristor crossbars. Nature Electronics, 1(1), 52.

    Article  Google Scholar 

  29. 29.

    Mark, L. P. (2010). HP and hynix to commercialize the memristor.

  30. 30.

    Member, A. S., Khiat, A., Prodromakis, T., & Senior Member. (2015). An RRAM biasing parameter optimiser (c) (pp. 1–6).

  31. 31.

    Mouttet, B. (2008). Proposal for memristors in signal processing. In International conference on nano-networks (pp. 11–13). Springer.

  32. 32.

    Mozaffari, S. N., Tragoudas, S., & Haniotakis, T. (2017). More efficient testing of metal-oxide memristor-based memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(6), 1018–1029.

    Article  Google Scholar 

  33. 33.

    Muthulakshmi, S., Dash, C. S., & Prabaharan, S. R. S. (2018). Memristor augmented approximate adders and subtractors for image processing applications: An approach. AEU-International Journal of Electronics and Communications, 91, 91–102.

    Article  Google Scholar 

  34. 34.

    Park, J., Jo, M., Lee, J., Jung, S., Lee, W., Kim, S., et al. (2011). Microelectronic engineering improved switching uniformity of a carbon-based conductive-bridge type ReRAM by controlling the size of conducting filament. Microelectronic Engineering, 88(6), 935–938.

    Article  Google Scholar 

  35. 35.

    Potrebić, M., Tošić, D., & Biolek, D. (2017). Rf/microwave applications of memristors. In Advances in memristors, memristive devices and systems (pp. 159–185). Cham: Springer.

  36. 36.

    Prezioso, M., Merrikh-Bayat, F., Hoskins, B. D., Adam, G. C., Likharev, K. K., & Strukov, D. B. (2015). Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature, 521(7550), 61.

    Article  Google Scholar 

  37. 37.

    Ravi, V., & Prabaharan, S. R. S. (2017). memristor based memories: Defects, testing, and testability techniques. Far East Journal of Electronics and Communications, 17(1), 105.

    Article  Google Scholar 

  38. 38.

    Ravi, V., & Prabaharan, S. R. S. (2018). Fault tolerant adaptive write schemes for improving endurance and reliability of memristor memories. AEU-International Journal of Electronics and Communications, 94, 392–406.

    Article  Google Scholar 

  39. 39.

    Ravi, V., & Prabaharan, S. R. S. (2018). Weak cell detection techniques for memristor-based memories. In Nanoelectronic materials and devices (pp. 101–110). Singapore: Springer.

  40. 40.

    Sarwar, S. S., Saqueb, S. A. N., Quaiyum, F., & Harun-Ur Rashid, A. B. M. (2013). Memristor-based nonvolatile random access memory: Hybrid architecture for low power compact memory design. IEEE Access, 1, 29–34.

    Article  Google Scholar 

  41. 41.

    Sawa, A. (2008). Resistive switching in transition metal oxides. Materials Today, 11(6), 28–36.

    Article  Google Scholar 

  42. 42.

    Strukov, D. B., Snider, G. S., Stewart, D. R., & Stanley Williams, R. (2008). The missing memristor found. Nature, 453(7191), 80.

    Article  Google Scholar 

  43. 43.

    Wang, X., Chen, Y., Xi, H., Li, H., & Dimitrov, D. (2009). Spintronic memristor through spin-torque-induced magnetization motion. IEEE Electron Device Letters, 30(3), 294–297.

    Article  Google Scholar 

  44. 44.

    Wei, Z., Kanzawa, Y., Arita, K., Katoh, Y., Kawai, K., Muraoka, S., Mitani, S., Fujii, S., Katayama, K., & Iijima, M. (2008). Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism. In Electron devices meeting, 2008. IEDM 2008. IEEE International (pp. 1–4). IEEE.

  45. 45.

    Yang, C., Choi, H., Park, S., Sah, M. P., Kim, H., & Chua, L. O. (2014). A memristor emulator as a replacement of a real memristor. Semiconductor Science and Technology, 30(1), 15007.

    Article  Google Scholar 

  46. 46.

    Yang, J., Joshua, M. X., Zhang, J. P., Strachan, F. M., Pickett, M. D., Kelley, R. D., et al. (2010). High switching endurance in TaOx memristive devices. Applied Physics Letters, 97(23), 232102.

    Article  Google Scholar 

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Ravi, V., Chitra, K. & Prabaharan, S.R.S. Variation-tolerant, low-power, and high endurance read scheme for memristor memories. Analog Integr Circ Sig Process 105, 83–98 (2020).

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  • Memristor
  • Endurance
  • Variation-tolerant
  • Low-power
  • Reliability