Variation-tolerant, low-power, and high endurance read scheme for memristor memories

Abstract

Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristor-based memory design. This paper presents a novel read scheme that achieves a non-destructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses built-in self-tuning circuitry to obtain the optimum amplitude and width of the refresh pulse required to completely retrieve the state of the memristor after the read cycle. As the scheme uses refresh pulse only when needed, the scheme saves nearly 50% of average power when compared with a conventional fixed pulse read method. The self-tuning circuits are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” model. The validation results prove that the proposed tuning circuitry achieves optimum refresh pulse size under various read disturbance faults.

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Ravi, V., Chitra, K. & Prabaharan, S.R.S. Variation-tolerant, low-power, and high endurance read scheme for memristor memories. Analog Integr Circ Sig Process 105, 83–98 (2020). https://doi.org/10.1007/s10470-020-01702-0

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Keywords

  • Memristor
  • Endurance
  • Variation-tolerant
  • Low-power
  • Reliability