Abstract
This paper presents a compact and robust opamp-free noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed NS SAR ADC adopts extra one passive feed-forward path summing in realizing second-order noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise sources of residue sampling and first-order integration on filter capacitors are obviated. It implements 4\(\times\) passive gain by capacitive charge-pump techniques that compensates the partial loss of residue voltage and relaxes the specifications of comparator. According to the behavioral modeling and simulation results, an ENOB of 16.88-bit is achieved based on a 10-bit DAC array, at the OSR of 16. Through utilizing the Monte Carlo simulation, the proposed ADC architecture is proven to be a robust system.
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Acknowledgements
The authors would like to thank J. Liu for useful discussion. This work was supported in part by the National Natural Science Foundation of China (Grant No. 61832007) and the National Key R&D Program of China (Grant No. 2018YFB1003304).
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Yi, P., Zhu, Z., Li, D. et al. An opamp-free second-order noise-shaping SAR ADC with 4\(\times\) passive gain using capacitive charge pump. Analog Integr Circ Sig Process 105, 125–133 (2020). https://doi.org/10.1007/s10470-020-01699-6
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DOI: https://doi.org/10.1007/s10470-020-01699-6