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A 17 MS/s SAR ADC with energy-efficient switching strategy


A simple energy-efficient switching procedure is proposed to reduce the total number of switches and facilitate the capacitors matching requirements in SAR ADCs. The main idea is that the coupling capacitor (CC) is utilized as the same as the unit one, which is applied for LSB charge production. After the reset phase, only the MSB capacitor is connected to the input potential, while the other experience either low and high reference potential; hence, a simplified switching strategy with 55% reduction in number of switches is retrieved. Post-layout simulation results confirm SNDR and ENOB of around 80 dB and 13 bit, respectively, at Nyquist input frequency when the conversion rate is 17 MS/s. In these conditions, FOMW and FOMS reach to 139.9 fJ/Conv-Step and 166.15 dB, respectively. Also, INL and DNL would experience the maximum level of + 0.95/− 0.58 LSB and + 0.63/− 0.74 LSB, respectively. The proposed ADC occupies active area of 1.7 mm2 and consumes around 20.6 mW power at 5 V supply and 17 MS/s conversion rate. Post-layout simulation results are performed using the HSPICE BSIM3 model of a 0.50 µm CMOS process.

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Mahdavi, S., Kazeminia, S. & Hadidi, K. A 17 MS/s SAR ADC with energy-efficient switching strategy. Analog Integr Circ Sig Process 103, 223–236 (2020).

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  • ADC
  • Low power
  • DAC
  • Comparator
  • High-resolution