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Mismatch suppression and noise reduction for SAR-ADC with Bayes estimation method

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Abstract

A statistical estimator based on Bayes Estimation theory is developed in this paper to simultaneously reduce capacitor mismatch and noise in a successive approximation register analogue-to-digital converter (SAR-ADC). Once the SAR-ADC has completed its quantization process, the residue voltage is available at the comparator input and can be estimated accurately using the Bayesian estimator. The ADC resolution is improved by subtracting the estimated residue from the digital output. The same technique of residue extraction is then used to estimate mismatches in the capacitive digital-to-analogue converter. A 15 dB improvement is observed in signal-to-noise-plus-distortion ratio by using the statistical estimator for a 10-bit SAR over a wide range of capacitance mismatch and ADC noise.

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Authors and Affiliations

  1. School of Electronic and Information Engineering, Beihang University, XueYuan Road No. 37, HaiDian District, Beijing, China

    Zhao Lei & Zhang Xiaolin

Authors
  1. Zhao Lei
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  2. Zhang Xiaolin
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Correspondence to Zhang Xiaolin.

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Lei, Z., Xiaolin, Z. Mismatch suppression and noise reduction for SAR-ADC with Bayes estimation method. Analog Integr Circ Sig Process 102, 379–388 (2020). https://doi.org/10.1007/s10470-019-01573-0

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  • DOI: https://doi.org/10.1007/s10470-019-01573-0

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