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A 2.4 GHz quadrature LC-VCO with combination of tunable pulse coupling and parallel coupling to optimize phase noise

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Abstract

This paper presents a pulse coupling method, in which two resonators are coupled periodically by a narrow pulse to reshape the current of coupling transistors. In order to guarantee that the output is in quadrature, the conventional parallel coupling is utilized, too. The noise from the coupling transistors is converted to the phase noise as the two coupling transistors are on the triode region. The narrow pulse is aligned with the time when two coupling transistors are both in the triode region, which provides a positive feedback path between in-phase port and anti-phase port to speed up the process of going through the triode region. Therefore, the noise from the coupling transistors is reduced, which is the essential reason of optimizing the phase noise. The proposed quadrature LC-VCO is fabricated in gf 130 nm CMOS process and the total power consumption is 6.1 mW from the supply voltage of 1.1 V. The measurement results show that the phase noise achieves \(-104.4\) dBc/Hz and \(-132.3\) dBc/Hz @ 100 kHz and 1 MHz offset, respectively. The core occupies 0.6 mm\(^{2}\) totally.

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Acknowledgements

This work is supported by the Youth Innovation Found, University of Science and Technology of China (No. WK6030000104).The authors would like to thank Information Science Laboratory Center of University of Science and Technology of China for software & hardware services.

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Authors and Affiliations

  1. Micro-/Nano-Electronic System Integration R&D Center, University of Science and Technology of China, Hefei, 230021, People’s Republic of China

    Na Xi & Fujiang Lin

  2. The Institute of Microelectronics of the Chinese Academy of Science, Beijing, 100029, People’s Republic of China

    Tianchun Ye

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  1. Na Xi
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  2. Tianchun Ye
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Correspondence to Na Xi.

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Xi, N., Ye, T. & Lin, F. A 2.4 GHz quadrature LC-VCO with combination of tunable pulse coupling and parallel coupling to optimize phase noise. Analog Integr Circ Sig Process 102, 205–212 (2020). https://doi.org/10.1007/s10470-019-01563-2

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  • DOI: https://doi.org/10.1007/s10470-019-01563-2

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