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On the design and analysis of a compact array with 1T1R RRAM memory element

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Abstract

In this paper, an analysis of a Verilog-A memristor model is discussed in order to be implemented in a 1T1R cell by exploring the characterization data of an OxRRAM device. The proposed analysis is done using mathematical formulation and verified by Spectre circuit simulator. The analysis is tested for a digital logic gate such as NAND gate for both, SET and RESET processes to perform read and write operations. Moreover, we explore diverse types of memory cells, two configurations are considered as a PROM and an EEPROM. Additionally, the implementation of the Verilog-A model on a crossbar array is discussed in details in terms of switching speed and the range of resistance. A comparison between the performances of various existing memory cells is also discussed. Our simulation results carry the desired nonlinear memristor fingerprint, the applicability to fit different switching behaviors. These results are verified by both electrical and experimental characterization data. We conclude that the proposed Verilog-A model is suitable for digitals circuits, crossbar arrays, low-power and high-density applications at the industrial levels.

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Authors and Affiliations

  1. Microelectronics and Instrumentation Lab, University of Monastir, Monastir, Tunisia

    Khaoula Mbarek, Faten Ouaja Rziga, Sami Ghedira & Kamel Besbes

  2. Center for Research in Microelectronics and Nanotechnology, Technopole, Sousse, Tunisia

    Kamel Besbes

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  1. Khaoula Mbarek
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  2. Faten Ouaja Rziga
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  3. Sami Ghedira
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  4. Kamel Besbes
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Correspondence to Faten Ouaja Rziga.

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Mbarek, K., Rziga, F.O., Ghedira, S. et al. On the design and analysis of a compact array with 1T1R RRAM memory element. Analog Integr Circ Sig Process 102, 27–37 (2020). https://doi.org/10.1007/s10470-019-01488-w

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  • DOI: https://doi.org/10.1007/s10470-019-01488-w

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