A Ku-band dual control path frequency synthesizer using varactorless Q-enhanced LC-type VCO
- 27 Downloads
This study focused on the design principle and implementation of a high-frequency, wide-range frequency synthesizer by using a dual control path phase-lock loop (PLL) and a varactorless oscillator controlled by inductive–capacitive (LC-type) voltage (i.e., a voltage-controlled oscillator, VCO). Without a varactor in the LC tank, the tuned-transducer oscillator with Q-enhanced functionality can easily arrive at the requirements of high-frequency wide-range low-noise operations. We utilized a difference tuned varactorless VCO to create two different KVCOs and applied it to a dual control path PLL architecture to obtain wide tuning range and more favorable phase noise. In addition, a high-speed current-mode logic divider was employed given its high speed (because of the use of a transformer inductor), extremely high operation frequency, and wide-range. The proposed PLL was assembled using the standard 0.13-μm CMOS technology on a 0.95 × 1.05 mm2 chip. The PLL dissipated 40 mW at a 1.2 V supply. The measurement of phase noise at 17.64 GHz was − 98.12 dBc/Hz at a 1 MHz offset.
KeywordsFrequency synthesizer Phase-lock loop (PLL) High-speed current-mode logic (FSCML) Quality factor Tuned transducer Varactorless Voltage-controlled oscillator (VCO)
This study was supported by Tunghai University, Taiwan, R.O.C. The author would like to thank the National Chip Implementation Center (CIC), Taiwan, R.O.C., for fabricating the chip. This study was also supported by the Ministry of Science and Technology (MOST 106-2221-E-029-028), Taiwan, R.O.C.
The study was funded by the Ministry of Science and Technology (Grant Number MOST 106-2221-E-029-028), Taiwan, R.O.C.
Compliance with ethical standards
Conflict of interest
The author declares there are no conflicts of interest.
Research involving human participants and/or animals
There were not any human participants and/or animals in the study.
There were not any informed consent in the study.
- 5.Yang, C.-Y., Chang, C.-H., & Weng, J.H. (2013). A 35-GHz frequency synthesizer using frequency doubling and phase rotating technology. In International symposium on communications and information technologies (ISCIT), Samui Island, Thailand (pp. 266–270).Google Scholar
- 6.Lin, L., & Gray, P. R. (2000). A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture. In IEEE international solid-state circuits conference digest of technical paper, San Francisco, CA (pp. 204–205, 458).Google Scholar
- 8.Sarang, K., Khayrollah, H., & Abdollah, K. (2015). A wide-range low-jitter PLL based on fast-response VCO and simplifed straightforward methodology of loop stabilization in integer-N PLLs. Journal of Circuits, Systems, and Computers, 24(7), 1550104-1–1550104-24.Google Scholar
- 9.Fong, N. H. W., Plouchart, J. O., Zamdmer, N., Liu, D., Wagner, L. F., Plett, C., et al. (2003). A 1-V 3.8-5.7-GHz wide-band VCO with differential tuned accumulation MOS varactors for common-mode noise rejection in CMOS SOI technology. IEEE Transactions on Microwave Theory and Techniques, 51(8), 1952–1959.CrossRefGoogle Scholar
- 10.Tang, Z., He, J., & Min, H. (2005). A low-phase-noise 1-GHz LC VCO differentially tuned by switched step capacitors. IEEE Asian Solide-State Circuits Conference (pp. 409–412). Taiwan: Hsinchu.Google Scholar
- 12.Piazza, F., & Huang, Q. (1997). A low power CMOS dual modulus prescaler for high-speed frequency synthesizer. IEICE Transactions on Electronics, E80-C(2), 314–319.Google Scholar
- 18.Kang, K., & Lin, F. (2010). A 20-GHz integer-N frequency synthesizer for 60-GHz transceivers in 90 nm CMOS. In Proceedings of the IEEE-ICUWB, Nanjing, China (pp. 1–4).Google Scholar
- 20.Adem, A., & Mohammed, I. (2004). CMOS PLLs and VCOs for 4G wireless. Dordrecht: Kluwer Academic Publishers.Google Scholar
- 23.Rylyakov, A., Tierno, J., Ainspan, H., Plouchart, J.O., Bulzacchelli, J., & Deniz, Z.T., et al. (2009). Bang-bang digital PLLs at 11 and 20 GHz with sub-200 fs integrated jitter for high-speed serial communication applications. In IEEE ISSCC digest of technical papers, San Francisco, CA (pp. 94–95).Google Scholar