A dynamic circuit design technique on the basis of true single phase logic is presented in this paper to minimize leakage power consumption. The circuit is comprehensively designed by incorporating a pair of diode transistor and a pair of stacked transistors. Active mode as well as idle mode power consumption and delay is analysed at low and high die temperature. 89–17% saving in power delay product is obtained for the same along with higher unity noise gain and reduced voltage bouncing noise. The analysis of the circuit also includes the investigation of voltage variation effect, process corner analysis and sizing effect analysis. The proposed technique is compared with several previously proposed dynamic circuit design techniques and it is found to have best power delay product. Further, it is implemented on 32 output decoder for enduring the technique. Comprehensive simulation using 90 nm technology in cadence specter, shows that the proposed design vanquish conventional and other previously proposed dynamic circuit design techniques in terms of power, delay, noise and robust against parameter and process corner variations.
This is a preview of subscription content, access via your institution.
Buy single article
Instant access to the full article PDF.
Tax calculation will be finalised during checkout.
Subscribe to journal
Immediate online access to all issues from 2019. Subscription will auto renew annually.
Tax calculation will be finalised during checkout.
Yeager, H. L., et al. (2004). Domino circuit topology. U. S. Patent 6784695
Gu, R. X., & Elmasry, M. I. (1999). Power dissipation analysis and optimization for deep submicron CMOS digital circuits. IEEE Journal of Solid-State Circuits, 31, 707–713.
Uyemura, J. (1993). A system perspective. Addison Wesley.
Gopalakrishnan, H., & Shiue, W. T. (2004). Leakage power reduction using self bias transistor in VLSI circuits. In IEEE workshop on microelectronics and electron devices (pp. 71–74).
Weste, N. H. E., Harris, D., & Banerjee, A. (2006). CMOS VLSI design: A circuits and systems perspective (3rd ed.). Delhi: Pearson Education.
Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2003). Digital integrated circuits: A design perspective (2nd ed.). Delhi: Pearson Education.
Radhakrishnan, D. (2001). Low-voltage low-power CMOS full adder. IEE Proceedings-Circuits, Devices and Systems, 148(1), 19–24.
Kang, S. M., & Leblebici, Y. (2003). CMOS digital integrated circuits, analysis design (3rd ed.). New York: McGraw Hill.
Kar, R., Mandal, D., Khetan, G., & Meruva, S. (2011) Low power VLSI circuit implementation using mixed static CMOS and domino logic with delay elements. In IEEE-SCOReD (pp. 370–374), December 19–20, 2011.
Meimand, H. M., & Roy, K. (2004). Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style. IEEE Transactions on Circuits and Systems I: Regular Papers, 51(3), 495–503.
Frustaci, F., Corsonello, P., Perri, S., & Cocorullo, G. (2008). High performance noise tolerant circuit techniques for CMOS dynamic logic. IET Circuits, Devices and Systems, 2(6), 537–548.
Moradi, F., et al. (2013). Domino logic design for high performance and leakage tolerant applications. Integration, the VLSI Journal, 46, 247–254.
Dadoria, A., et al. (2015). A novel high-performance leakage-tolerant, wide fan-in domino logic circuit in deep-submicron technology. Circuits and Systems, 6, 103.
Manzoor, M., Verma, S., Singh, T., & Manzoor, M. (2016). Various techniques to overcome noise in dynamic CMOS logic. Indian Journal of Science and Technology. https://doi.org/10.17485/ijst/2016/v9i22/90152.
Weste, N., & Eshraghian, K. (1994). Principles of CMOS VLSI design. Boston: Addison-Wesley.
Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2004). Digital integrated circuits (2nd ed.). Delhi: Prentice-Hall of India Private Limited.
Ji-Ren, Y., Karlsson, I., & Svensson, C. (1987). A ture single-phase-clock dynamic CMOS circuit technique. IEEE Journal of Solid-State Circuits, 22, 899–901.
Larsson, P., & Svensson, C. (1994). Impact of clock slope on true single phase clocked (TSPC) CMOS circuit. IEEE Journal of Solid-State Circuits, 29(6), 723–726.
Cheng, K. H., & Huang, Y. C. (2000). The non-full voltage swing TSPC (NSTSPC) logic design. IEEE 2000.
Kim, S., Ziesler, C. H., & Papaeftymiou, M. C. (2003). A true single phase energy recovery multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(2), 194–207.
Hernandez, F. M., Aranda, M. L., & Champac, V. (2006). Noise tolerance improvement in dynamic CMOS logic circuits. IEE Proceedings-Circuits, Devices and Systems, 153(6), 565–573.
Asati, A., & Chandrashekhar, (2009). A high speed pipelined dynamic circuit implementation using modified TSPC logic design style with improved performance. International Journal of Recent Trends in Engineering, 1(3), 191.
Sharma, P., Chandel, R., & Sarkar, S. (2011). Noise tolerant technique in super and sub-threshold region of TSPC logic. Special Issue of IJCA-ICEICE, 5, 25–28.
Mitra, A. (2014). Design and analysis of low power high speed 1-bit full adder cell based on TSPC logic with multithreshold CMOS. World Academy of Science, Engineering and Technology, 8(1), 185–188.
Rastogi, R., & Pandey, S. (2015). Implementing low power dynamic adder in MTCMOS technology. In IEEE conference—ICECS.
Wey, I. C., et al. (2015). Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique. International Journal of Circuit Theory and Applications, 43, 584–865.
Taur, Y., & Ning, T. H. (1998). Fundamentals of modern VLSI devices. Cambridge: Cambridge University Press.
Yeo, K.-S., & Roy, K. (2004). Low voltage, low power VLSI subsystems. New York: McGraw-Hill.
Verma, P., Sharma, A. K., et al. (2016). Estimation of leakage power and delay in CMOS circuits using parametric variation. Perspectives in Science, 8, 760–763.
Flandre, D., Bulteel, O., Gosset, G., Rue, B., & Bol, D. (2012). Ultra-low-power analog and digital circuits and microsystems using disruptive ultra-low-leakage design techniques. In ICCDCS
Verma, P., Sharma, A. K., Noor, A., & Pandey, V. S. (2017). SDTSPC-technique for low power noise aware 1-bit full adder. Analog Integrated Circuits and Signal Processing, 92(2), 303–314.
Tang, F., Zhu, K., Gan, Q., & Tang, J. G. (2008). Low-noise and power dynamic logic circuit design based on semi-dynamic buffer. In IEEE-ASID, 2nd international conference.
Larsson, P., & Svensson, C. (1994). Noise in digital dynamic CMOs circuits. IEEE Journal of Solid-State Circuits, 29(6), 656–662.
Peiravi, A., Moradi, F., & Wisland, D. T. (2009). Leakage tolerant, noise immune domino logic for circuit design in the ultra deep submicron CMOS technology for high fan-in gates. Journal of Applied Sciences, 9(2), 392–396.
Oklobdzija, V. G. (2003). Clocking and clocked storage elements in a multigiga-hertz environment. IBM Journal of Research and Development, 47, 567–584.
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
About this article
Cite this article
Verma, P., Sharma, A.K., Noor, A. et al. A novel approach for noise tolerant energy efficient TSPC dynamic circuit design. Analog Integr Circ Sig Process 100, 119–131 (2019). https://doi.org/10.1007/s10470-019-01444-8
- Ultra low power
- True single phase
- Unity noise gain
- Bouncing noise